Performance constrained multi-application network on chip core mapping

Reddy, B. Naresh Kumar; Kishan, Dharavath; Vani, B. Veena

doi:10.1007/s10772-019-09636-3

Cited by 23 publications

(4 citation statements)

References 26 publications

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“…Initially, high performance (high penetration networks and low latency) was a major goal. For this reason, most of the previous works in NoC projects focus on performance parameters only [24][25][26]. However, with the growing demand for network bandwidth and higher throughput, the power used by the network connection is also becoming a major concern.…”

Section: Power Estimationmentioning

confidence: 99%

Efficient Power Estimation Using DSENT for 3D-Mesh on Chip Optic Communication Network

Ahmed,

Ambudka,

Yadav

2024

ISI

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The Network-on-Chip (NoC) stands as a potent solution for achieving heightened performance, efficient communication, and dependability in the migration of Very-Large Scale Integration (VLSI) architecture toward deep submicron technology, when contrasted with conventional connectivity networks. Considerable research endeavours have been allocated to diverse facets of NoCs, encompassing topology, routing algorithms, traffic behaviours, power management, and fundamental mapping. This paper explores the power consumption efficiency of Parameterized Path-Based, Randomized, Oblivious, Minimal for 3D Mesh (PROM3D) routing and ZXY routing algorithms for various traffic patterns like transpose, bit shuffle, and random traffic with the help of the integrated DSENT network model. The PROM3D routing algorithm selects a path randomly from all possible minimal pathways between the source and destination, whereas ZXY is a layer-based routing method. The Design Space Exploration of Network (DSENT) tool is used with the NoC Interconnect Routing and Applications Modeling (NIRGAM) simulator in experiments to measure the power consumption. The findings indicate that, within the 3D-Mesh environment, the ZXY routing algorithm exhibits a 0.02% of variation in power consumption while in saturation on varying loads for various traffic patterns in comparison to the PROM3D algorithm.

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Section: Power Estimationmentioning

confidence: 99%

Efficient Power Estimation Using DSENT for 3D-Mesh on Chip Optic Communication Network

Ahmed,

Ambudka,

Yadav

2024

ISI

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“…The regular cores normally execute the task of a specified application, the spare cores are additional cores that can be employed in case of failure of either regular or manager core, and the manager cores are used to track and manage all processing cores. Besides, when a processing core fails, the manager core performs the task migration [13].…”

Section: Network-on-chip Architecturementioning

confidence: 99%

Network-on-Chip Topologies: Potentials, Technical Challenges, Recent Advances and Research Direction

Alimi¹,

Patel²,

Aboderin³

et al. 2022

Network-on-Chip - Architecture, Optimization, and Design Explorations

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Integration technology advancement has impacted the System-on-Chip (SoC) in which heterogeneous cores are supported on a single chip. Based on the huge amount of supported heterogeneous cores, efficient communication between the associated processors has to be considered at all levels of the system design to ensure global interconnection. This can be achieved through a design-friendly, flexible, scalable, and high-performance interconnection architecture. It is noteworthy that the interconnections between multiple cores on a chip present a considerable influence on the performance and communication of the chip design regarding the throughput, end-to-end delay, and packets loss ratio. Although hierarchical architectures have addressed the majority of the associated challenges of the traditional interconnection techniques, the main limiting factor is scalability. Network-on-Chip (NoC) has been presented as a scalable and well-structured alternative solution that is capable of addressing communication issues in the on-chip systems. In this context, several NoC topologies have been presented to support various routing techniques and attend to different chip architectural requirements. This book chapter reviews some of the existing NoC topologies and their associated characteristics. Also, application mapping algorithms and some key challenges of NoC are considered.

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“…Bat mapping algorithm was introduced in [19] for mapping on NoC strategy. But the algorithm failed to resolve the multiobjective problems during the mapping process.…”

Section: Related Workmentioning

confidence: 99%

Multicriteria Deming Regressive African Buffalo Optimized Mapping for 3D NoC Architecture Design

Sushma

Alagarsamy

Lakshminarayanan

et al. 2022

Mathematical Problems in Engineering

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Purpose. Networks-on-Chip (NoC) is a network-based communication between operating cores and intellectual property (IP) cores integrated on the same chip. An efficient design of NoC ensures high-speed data transfer and minimum essential connections in large-scale multicore, low power applications. Design/methodology/approach. A unique technique called Multicriteria Deming Regressive African Buffalo Optimized Mapping Weighted Directive Graph Theory (MDRABOMWDGT) is introduced for an efficient Network-on-Chip architecture design. The main aim of the proposed technique is to find efficient operating cores integrated on the chip with minimum time. Initially, a set of IP cores are listed with their connections from the benchmark dataset. Then Multicriteria Deming Regressive African Buffalo Optimization is applied to the topology for mapping strategy on 3D NoC, with communication metrics such as throughput, latency, and computation time. The optimization technique initializes the population of cores in search space. For each core in the network, communication metrics are measured; then Deming regression is applied to analyze multicriteria functions for minimizing computation time. Further, fitness is measured to get an optimal IP core for improving the performance of mapping in 3D NoC. Findings. Comprehensive experimental evaluation is conducted using a benchmark dataset, communication metrics are measured, and results show significant improvement in performance with respect to energy parameters compared to state-of-the-art works. Originality/value. The mapping strategy for 3D NOC is developed and the results are compared with the state-of-the-art techniques.

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Performance constrained multi-application network on chip core mapping

Cited by 23 publications

References 26 publications

Efficient Power Estimation Using DSENT for 3D-Mesh on Chip Optic Communication Network

Efficient Power Estimation Using DSENT for 3D-Mesh on Chip Optic Communication Network

Network-on-Chip Topologies: Potentials, Technical Challenges, Recent Advances and Research Direction

Multicriteria Deming Regressive African Buffalo Optimized Mapping for 3D NoC Architecture Design

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