Performance-driven register insertion in placement

Abstract

As the CMOS technology is scaled into the dimension of nanometer, the clock frequencies and die sizes of ICs are shown to be increasing steadily [5]. Today, global wires that require multiple clock cycles to propagate electrical signal are prevalent in many deep sub-micron designs. Efforts have been made to pipeline the long wires by introducing registers along these global paths, trying to reduce the impact of wire delay dominance [2,8].The technique of retiming to relocate registers in a circuit without affecting the circuit functionality can be applied in this problem. Though the problem of retiming with gate and wire delay has been studied recently [17,1], the placement of registers after retiming is a new challenge. In this paper, we study the problem of realizing a retiming solution on a global netlist by inserting registers in the placement to achieve the target clock period. In contrast to many previous works [16,11] that performed simple calculations to determine the positions of the registers, our proposed algorithm can preserve the given clock period and utilize as few registers as possible in the realization. What is more, the algorithm is shown to be optimal for nets with 4 or fewer pins and this type of nets constitutes over 90% of the nets in a sequential circuit on average.Using the ISCAS89 benchmark suite, we tested our algorithm with a 0.35µm CMOS standard cell library, and Silicon Ensemble was used to layout the design with row utilization of 50%. Experimental results showed that our algorithm can find the best sharing of registers for a net in most of the cases, i.e., using the minimum number of registers while preserving the target clock period, within a minute running on an Intel Pentium IV 1.5GHz PC with 512MB RAM.

Optimal wire retiming without binary search

“…Inside the iteration, the algorithm either changes r (lines [18][19] or successfully reduces T (lines 24-25). For the former, an r adjustment and an initialization under the new r are immediately followed, which will keep (1)- (4) for the next iteration.…”

An efficient retiming algorithm under setup and hold constraints

“…Each vertex v C V represents a gate and each edge period [2,7], and retiming is again a promising technique that could e e E represents a signal passing from one gate to another-with gate be leveraged [1,11,12,26,28]. lays d, this model is identical to the one used by Leiserson and Saxe [10].…”

Throughput-driven floorplanning with wire pipelining

“…Concerning the physical synthesis aspects, Cong and Lim [7], and more recently Lu and Koh [8] and Chu et al [9], formulate the problem of wire pipelining as one of retiming, therefore assuming that latches or flip-flops can be moved from logic blocks to interconnects. In a recent paper, Tong and Young [10] proposed a method for register placement along global wires, given a retiming solution. However, as already noticed in the introduction, while optimal, retiming can only be applied if logic blocks are described at least at RT level and either the logic description or the post-synthesis netlist is available.…”