Performance-driven simultaneous place and route for row-based FPGAs

Abstract

Sequential place and route tools for FPGAs are inherently weak at addressing both wirability and timing optimizations. This is primarily due to the difficulty in predicting these at the placement level. A new performance-driven simultaneous placement / routing technique has been developed for row-based designs. Up to 28% improvements in timing and 33% in wirability have been achieved over a traditional sequential place and route system in use at Texas Instruments for several MCNC benchmark examples.

Timing-driven placement for FPGAs

“…In this section we discuss some existing timingdriven placement tools, starting with two FPGA-specific placement tools, PROXI [4] and Triptych [5], followed by two standard cell placement tools, Timberwolf [6], and SPEED [7].…”

“…The PROXI [4] algorithm is a Simulated Annealing based timing-driven placement algorithm that is designed for FPGAs. This algorithm has good results but it is very computationally intensive.…”

“…The algorithm achieves an 8% -15% improvement in delay compared to the Xilinx XACT 5.0 place and route system; however it has a significant disadvantage in CPU compile time, ranging from 6 times for the smallest design (a 12 x 12 array) to 11 times for the largest design (a 16 x 16 array). The computational complexity of this algorithm (while not given in [4]) appears to be O(n 3) from the data they present, making it infeasible for large circuits.…”

“…The most accurate technique would be to route each proposed placement and extract the routed delay of each connection as [4] did, but this approach requires unacceptable amounts of CPU time. Instead, we create a "delay profile" of an FPGA that is used to rapidly evaluate the delay of each connection in the circuit given the placement of its terminals.…”

FPGA routing and routability estimation via Boolean satisfiability

“…One such approach is described in [Nag94,Nag95], which attack both the placement and routing problems simultaneously by allowing placement changes to be evaluated for their routability and ultimate net delay using an actual, incremental detailed router. [Wu93] observes that simplified variants of the detailed routing problem for FPGAs are reducable to the 2D interval packing problem, and to the graph coloring problem.…”