Timing-driven placement for FPGAs

Marquardt, Alexander; Betz, Vaughn; Rose, Jonathan

doi:10.1145/329166.329208

Cited by 215 publications

(165 citation statements)

References 9 publications

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“…Our algorithm uses a simulated annealing-based optimization engine [21][1] [18]. We first perform an initial clustering on the mapped netlist, and then generate a random placement of the clustered netlist.…”

Section: Overviewmentioning

confidence: 99%

“…[18]) convert timing information into net weight and optimize a weighted function of all nets. The basic idea of net weighting is to assign higher weights to timing critical nets and lower weights to non-critical nets.…”

Section: Path Counting-based Net Weightingmentioning

confidence: 99%

“…We first analyze the computation complexity of VPR's placement engine T-VPlace [18]. The timing analysis is performed once per temperature change, which is an O(n) operation.…”

Section: Complexity Analysismentioning

confidence: 99%

See 2 more Smart Citations

Simultaneous Timing Driven Clustering and Placement for FPGAs

Chen

Cong

2004

Field Programmable Logic and Application

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Abstract. Traditional placement algorithms for FPGAs are normally carried out on a fixed clustering solution of a circuit. The impact of clustering on wirelength and delay of the placement solutions is not well quantified. In this paper, we present an algorithm named SCPlace that performs simultaneous clustering and placement to minimize both the total wirelength and longest path delay. We also incorporate a recently proposed path counting-based net weighting scheme [16]. Our algorithm SCPlace consistently outperforms the state-of-the-art FPGA placement flow (T-VPack + VPR) with an average reduction of up to 36% in total wirelength and 31% in longest path delay.

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Section: Overviewmentioning

confidence: 99%

Section: Path Counting-based Net Weightingmentioning

confidence: 99%

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Simultaneous Timing Driven Clustering and Placement for FPGAs

Chen

Cong

2004

Field Programmable Logic and Application

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“…Timing driven (TD) placement algorithms can be divided into 3 categories. 1) partition-based, like [9,12], 2) simulated annealing (SA) based, like [11,15], and 3) analytical [8]. Circuit timing optimization is basically a pathbased problem, though it is impractical to track delays of all paths, since their numbers are generally exponential in circuit size [8].…”

Section: Introductionmentioning

confidence: 99%

A Network-Flow Approach to Timing-Driven Incremental Placement for ASICs

Dutt¹,

Ren$^{²,

Yuan³

et al. 2006

2006 IEEE/ACM International Conference on Computer Aided Design

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We present a novel incremental placement methodology called FlowPlace for significantly reducing critical path delays of placed standard-cell circuits. FlowPlace includes: a) a timing-driven (TD) analytical global placer TAN that uses accurate delay functions and minimizes a combination of linear and quadratic objective functions; b) a network flow based detailed placer TIF that has new and effective techniques for performing TD incremental placement and satisfying rowlength (white space) constraints. We have obtained results on three sets of benchmarks: i) TD versions of the ibm benchmark suite that we have constructed; ii) benchmarks used in TD-Dragon; iii) the Faraday benchmarks. Results show that starting with Dragon-placed circuits, we are able to obtain up to 34% and an average of 18% improvement in critical path delays, at an average of 17.5% of the run-time of the Dragon placer. Starting with a state-of-the-art TD placer TD-Dragon, for the TD-Dragon benchmarks we obtain up to about 10% and an average of 4.3% delay improvement with 12% of TD-Dragon's run times; this is significant as we are extracting performance improvements from a performanceoptimized layout. Wire length deterioration on the average over all benchmark suites is less than 8%.

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“…On the other hand, annealing-based placement algorithms generate high quality results at the expense of runtime (e.g., [7], [10]). It would be desirable to achieve the lower computational complexities of divide-and-conquer methods (i.e., partitioningbased / hierarchical) while obtaining the high qualities of annealing-based placement techniques.…”

Section: Introductionmentioning

confidence: 99%

Fast timing-driven partitioning-based placement for island style FPGAs

Maidee¹,

Ababei²,

Bazargan³

Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)

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In this paper we propose a partitioning-based placement algorithm for FPGAs. The method incorporates simple, but effective heuristics that target delay minimization. The placement engine incorporates delay estimations obtained from previously placed and routed circuits using VPR [6]. As a result, the delay predictions during placement more accurately resemble those observed after detailed routing, which in turn leads to better delay optimization. An efficient terminal alignment heuristic for delay minimization is employed to further optimize the delay of the circuit in the routing phase. Simulation results show that the proposed technique can achieve comparable circuit delays (after routing) to those obtained with VPR while achieving a 7-fold speedup in placement runtime.

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Timing-driven placement for FPGAs

Cited by 215 publications

References 9 publications

Simultaneous Timing Driven Clustering and Placement for FPGAs

Simultaneous Timing Driven Clustering and Placement for FPGAs

A Network-Flow Approach to Timing-Driven Incremental Placement for ASICs

Fast timing-driven partitioning-based placement for island style FPGAs

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