Performance efficient FPGA implementation of parallel 2-D MRI image filtering algorithms using Xilinx system generator

Hasan, Sami; Yakovlev, Alex; Boussakta, S.

doi:10.1109/csndsp16145.2010.5580315

Cited by 19 publications

(5 citation statements)

References 12 publications

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“…FPGA supports the supply/acquisition to/from FPGAs with the computer communication interface. The interface also serves the goal of debugging as it is easy to understand data [1][2][3][4][5][6]. For this reason, the RS-232 communication interface is used.…”

Section: Results Analysismentioning

confidence: 99%

“…This discovery further pushed this work to incorporate configurability on-thefly. A comparison is made with the latest developments related to the biomedical signal processing applications, followed by a cycle and gate number of the profile [1][2][3][4]. It is observed that minimum gate number for the SAC architecture is reported among dedicated or similarly aimed software implementations.…”

Section: Results Analysismentioning

confidence: 99%

“…It's obtained by knowing the grayscale in the pixels of the captured image. Mutual Information is the recognized image capacity method for intensity-based multimodality image registration [1,2]. In a usual image registration system, a relationship measurements method is presented.…”

Section: Introductionmentioning

confidence: 99%

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Histogram Computation with a Reconfigurable Memory Based Fast VLSI Architecture

Ramesh

Kumar

2022

Advances in Transdisciplinary Engineering

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Computation of histogram is the primary work that used in digital image processing systems. Mutual Information is the best measurement that also used for image registration. Calculation of the mutual information requires obtaining separate and combining histogram of the two images. By the increase of the histogram size, the demand for the hardware resource for the computation of the histogram is increased. This paper about the computation of the memory-based VLSI architecture has been shown. The architecture of the computation of the histogram is existed by using the plotting in the field programmable field array. Parallelization of histogram functions is a major problem due to memory collisions. So, to avoid these collisions there is a new technique called parallel histogram computation used. To implement the parallel histogram, it is requiring dual–ported memory. By making the computation of the histogram fast, there are several benefits obtained. Some of the examples are texture classification, image compression, etc shown in this manuscript.

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Section: Results Analysismentioning

confidence: 99%

Section: Results Analysismentioning

confidence: 99%

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Histogram Computation with a Reconfigurable Memory Based Fast VLSI Architecture

Ramesh

Kumar

2022

Advances in Transdisciplinary Engineering

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“…FPGAs are increasingly used in modern imaging applications image filtering [5][6], medical imaging [7][8], image compression and wireless communication [9]. The rest of the paper is organized as follows.…”

Section: Introductionmentioning

confidence: 99%

Real Time Hardware Co - Simulation for Image Processing Algorithms Using Xilinx System Generator

Alareqi¹,

Elgouri²,

Mateur³

et al. 2015

ijeei

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The implementation of digital image processing required detailed knowledge of both hardware design and hardware description languages. This paper presents an efficient approach for the implementation of real time hardware digital image processing algorithms without requiring detailed knowledge of hardware design and hardware description languages. The purpose of this work is to achieve a real time hardware implementation with higher performance in both size and speed. It focuses on the implementation of an efficient architecture for image processing algorithms like segmentation (threshold) and contrast stretching by using the fewest possible system generator blocks for DSP tool, which integrates itself with the MATLAB based Simulink graphics environment and relieves the user of the textual HDL programming. While Past research has shown that the Image enhancement techniques on FPGA based on the Xilinx System Generator. This study connect between image histogram and Image enhancement techniques depending on the type of enhancement required. This paper describes also the methodology for implementing real-time DSP applications on FPGA and concept of hardware software co-simulation for digital image processing by using the Mathworks model-based design tool Simulink / Xilinx System Generator (XSG). Performances of efficient architectures are implemented on FPGA Virtex5 (XUPV5-LX110T).

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“…On the other hand, parallel multidimensional filtering algorithms (Boussakta, 1999;Wing-Kuen Ling, 2002), to be efficiently implemented, demand high computational performance per Watt at maximum sampling frequency (Hasan et al, 2010). Consequently, this study proposes system-level implementation of parallel reconfigurable architectures for nine different 2-D MRI digital filtering algorithms: Edge, Sobel X, Sobel Y, Sobel X-Y, Blur, Smooth, Sharpen, Gaussian and Beta (HYB).…”

Section: Introductionmentioning

confidence: 99%

FPGA-Based Architecture for a Generalized Parallel 2-D MRI Filtering Algorithm

U.¹

2011

American Journal of Engineering and Applied Sciences

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Problem statement: Current Neuroimaging developments, in biological research and diagnostics, demand an edge-defined and noise-free MRI scans. Thus, this study presents a generalized parallel 2-D MRI filtering algorithm with their FPGA-based implementation in a single unified architecture. The parallel 2-D MRI filtering algorithms are Edge, Sobel X, Sobel Y, Sobel X-Y, Blur, Smooth, Sharpen, Gaussian and Beta (HYB). Then, the nine MRI image filtering algorithm, has empirically improved to generate enhanced MRI scans filtering results without significantly affecting the developed performance indices of high throughput and low power consumption at maximum operating frequency. Approach: The parallel 2-d MRI filtering algorithms are developed and FPGA implemented using Xilinx System Generator tool within the ISE 12.3 development suite. Two unified architectures are behaviorally developed, depending on the abstraction level of implementation. For performance indices comparison, two Virtex-6 FPGA boards, namely, xc6vlX240Tl-1lff1759 and xc6vlX130Tl-1lff1156 are behaviorally targeted. Results: The improved parallel 2-D filtering algorithms enhanced the filtered MRI scans to be edge-defined and noise free grayscale imaging. The single architecture is efficiently prototyped to achieve: high filtering performance of (11230 frames/second) throughput for 64*64 MRI grayscale scan, minimum power consumption of 0.86 Watt with a junction temperature of 52°C and a maximum frequency of up to (230 MHz). Conclusion: The improved parallel MRI filtering algorithms which are developed as a single unified architecture provide visibility enhancement within the filtered MRI scan to aid the physician in detecting brain diseases, e.g., trauma or intracranial haemorrhage. The high filtering throughput is feasibly nominee the nine parallel MRI filtering algorithms for applications such as real-time MRI potential future applications. Future Work: a set of parallel 3-D fMRI filtering algorithms will be investigated to be developed and fast FPGA prototyped for future research project

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Performance efficient FPGA implementation of parallel 2-D MRI image filtering algorithms using Xilinx system generator

Cited by 19 publications

References 12 publications

Histogram Computation with a Reconfigurable Memory Based Fast VLSI Architecture

Histogram Computation with a Reconfigurable Memory Based Fast VLSI Architecture

Real Time Hardware Co - Simulation for Image Processing Algorithms Using Xilinx System Generator

FPGA-Based Architecture for a Generalized Parallel 2-D MRI Filtering Algorithm

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