2017
DOI: 10.1109/tnano.2017.2683201
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Performance Enhancement in N-Channel Organic Field-Effect Transistors Using Ferroelectric Material as a Gate Dielectric

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Cited by 10 publications
(6 citation statements)
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“…When OFETbased memories are fabricated using the traditional planar architecture, their performance (particularly, driving force and operating speed) is generally limited by a few factors, including their relatively long channel lengths, the low intrinsic mobility of OSC materials, and the charged defects arising at the I/S interface. [341][342][343]361] In some cases, the mechanical stability of POFETs also becomes questionable since their bending/flexing has been reported to induce small cracks in the OSC layer, which inhibits the transport of lateral charge transport. [88,205] Given these circumstances, fabrication of OFETs in the vertical architecture (viz.…”
Section: Discussion and Comparison Between Pofet-and Vofet-based Flex...mentioning
confidence: 99%
See 1 more Smart Citation
“…When OFETbased memories are fabricated using the traditional planar architecture, their performance (particularly, driving force and operating speed) is generally limited by a few factors, including their relatively long channel lengths, the low intrinsic mobility of OSC materials, and the charged defects arising at the I/S interface. [341][342][343]361] In some cases, the mechanical stability of POFETs also becomes questionable since their bending/flexing has been reported to induce small cracks in the OSC layer, which inhibits the transport of lateral charge transport. [88,205] Given these circumstances, fabrication of OFETs in the vertical architecture (viz.…”
Section: Discussion and Comparison Between Pofet-and Vofet-based Flex...mentioning
confidence: 99%
“…The characteristics above play an active role in reducing the operating speed and deteriorating the driving force of planar ferroelectric OFET NVMs. [342,343] In the case of planar devices prepared on flexible substrates, mechanical bending can produce small cracks in the OSC layer, hindering the lateral transport of charge carriers. [88,205] Considering these limitations, researchers have started considering the fabrication of ferroelectric OFET memories in vertical architecture.…”
Section: Application In Ferroelectric Memoriesmentioning
confidence: 99%
“…The second one is the solution-process method. Printed TFTs with high on/off ratios and low operation voltages could be obtained when using high- k polymer dielectrics such as poly­(vinylidenefluoride trifluoroethylene) P­(VDF-TrFE) or high-capacitance electrolytes as the dielectric inks. , Unfortunately, these devices exhibited large hysteresis for P­(VDF-TrFE) TFT devices and poor bias stress stability for high-capacitance electrolyte TFT devices. Using thermal oxidation or oxygen plasma treatment to form ultrathin metal oxide dielectric layers above active metals [aluminum (Al) and yttrium (Y)] is the third way, which is a large-area, simple, and low-cost method to prepare the dielectric layers (especially for the preparation of AlO x ). , Some groups have ever tried to use ultrathin aluminum oxide dielectric layers produced by oxygen plasma or room-temperature oxidation to fabricate the solution-processable or printed TFTs. , Unfortunately, these TFT devices showed high leakage currents up to 10 –8 A.…”
Section: Introductionmentioning
confidence: 99%
“…However, transistor devices employing these high‐ k dielectrics suffer from large bias hysteresis and large energetic disorder due to their ferroelectric nature and highly polarized interface. [ 4–9 ] Alternate dielectric engineering approaches such as polymer blend [ 10,11 ] and bilayer polymer [ 12,13 ] dielectrics have been employed in combination with low‐ k polymer dielectrics to curb these drawbacks. However, fabricated devices based on these techniques showed relatively lower charge‐carrier mobility compared to single‐layer high‐ k polymer gate dielectrics.…”
Section: Introductionmentioning
confidence: 99%