2015 IEEE International Symposium on Nanoelectronic and Information Systems 2015
DOI: 10.1109/inis.2015.68
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Performance Enhancement of Dopingless Tunnel-FET Based on Ge-Source with High-k

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Cited by 3 publications
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“…JLTFETs also include inferior I on and ambipolar behavior. To overcome these problems, different methods have been investigated, such as: using heterostructures at source/channel interfaces [37][38][39][40][41], the assumption of gate workfunction engineering [42][43][44][45], the adoption of hetero-gate dielectrics [46][47][48][49], using Gaussian-doping profiles [22,50,51], applying source pockets [52], the consideration of strain engineering [53,54], using ferroelectric insulators [40], and drain workfunction engineering for DLTFET [55,56].…”
Section: Introductionmentioning
confidence: 99%
“…JLTFETs also include inferior I on and ambipolar behavior. To overcome these problems, different methods have been investigated, such as: using heterostructures at source/channel interfaces [37][38][39][40][41], the assumption of gate workfunction engineering [42][43][44][45], the adoption of hetero-gate dielectrics [46][47][48][49], using Gaussian-doping profiles [22,50,51], applying source pockets [52], the consideration of strain engineering [53,54], using ferroelectric insulators [40], and drain workfunction engineering for DLTFET [55,56].…”
Section: Introductionmentioning
confidence: 99%