Performance Evaluation of an SIMD Architecture with a Multi-bank Vector Memory Unit

Chang, Hoseok; Cho, Junho; Sung, Wonyong

doi:10.1109/sips.2006.352558

Cited by 5 publications

(4 citation statements)

References 12 publications

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“…Additional sub-word data manipulation instructions are needed to prepare vector operands [43] for vector ALUs. We have implemented a three operand shuffle instruction that can generate the output as any combination of the sub-words of two input operands, while the third operand, sets selection criteria either through an immediate value or a register as seen in Figure 6.…”

Section: E Ex-stage: Alumentioning

confidence: 99%

Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices

Gautschi

Schiavone

Traber

et al. 2017

IEEE Trans. VLSI Syst.

375

270

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Endpoint devices for Internet-of-Things not only need to work under extremely tight power envelope of a few milliwatts, but also need to be flexible in their computing capabilities, from a few kOPS to GOPS. Near-threshold (NT) operation can achieve higher energy efficiency, and the performance scalability can be gained through parallelism. In this paper we describe the design of an opensource RISC-V processor core specifically designed for NT operation in tightly coupled multi-core clusters. We introduce instructionextensions and microarchitectural optimizations to increase the computational density and to minimize the pressure towards the shared memory hierarchy. For typical data-intensive sensor processing workloads the proposed core is on average 3.5× faster and 3.2× more energy-efficient, thanks to a smart L0 buffer to reduce cache access contentions and support for compressed instructions. SIMD extensions, such as dot-products, and a built-in L0 storage further reduce the shared memory accesses by 8× reducing contentions by 3.2×. With four NT-optimized cores, the cluster is operational from 0.6 V to 1.2 V achieving a peak efficiency of 67 MOPS/mW in a low-cost 65 nm bulk CMOS technology. In a low power 28 nm FDSOI process a peak efficiency of 193 MOPS/mW (40 MHz, 1 mW) can be achieved.Index Terms-Internet-of-Things, Ultra-low-power, Multi-core, RISC-V, ISA-extensions.

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Section: E Ex-stage: Alumentioning

confidence: 99%

Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices

Gautschi

Schiavone

Traber

et al. 2017

IEEE Trans. VLSI Syst.

375

270

View full text Add to dashboard Cite

show abstract

“…Although the SIMdD supports non-aligned and irregular data access efficiently, it is based on costly multi-port memory. The other memory architectures such as multibank scratch-pad memory and dual-bank cache memory are studied in [8] [5]. The multi-bank memory units perform non-aligned and stride access efficiently, while the dual-bank cache can efficiently support only non-aligned access.…”

Section: Related Workmentioning

confidence: 99%

“…x [8] x+7 x+3 x+0 x+8 Figure 6: Index register-based 4-port memory compiler framework. Although this scheme needs an extra software overhead, its operation at runtime is simple and efficient because it provides a separate address space to the packing buffer and there is no need of concerning the coherency problem.…”

Section: Irregular Data Access and Hard-ware Supportmentioning

confidence: 99%

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Efficient vectorization of SIMD programs with non-aligned and irregular data access hardware

Chang

Sung

2008

Proceedings of the 2008 International Conference on Compilers, Architectures and Synthesis for Embedded Systems

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Automatic vectorization of programs for partitioned-ALU SIMD (Single Instruction Multiple Data) processors has been difficult because of not only data dependency issues but also non-aligned and irregular data access problems. A nonaligned or irregular data access operation incurs many overhead cycles for data alignment. Moreover, this causes difficulty in efficient code generation and hinders automatic vectorization. In this paper, we employ special memory access hardware for improving the performance of SIMD processors; one is the split line buffer and the other is the packing buffer. The former solves the non-aligned memory access problem, while the latter simplifies irregular and stride data access. The addition of these hardware units not only requires very small changes to the instruction set architecture but also contributes to the significant performance improvement by vectorizing more loops and reducing the overhead cycles. We have also developed an auto-vectorization compiler which utilizes these special hardware units. Experiments have been conducted to compare the proposed method with the conventional one, which show 50% increase in the number of vectorized loops and 77% increase in the total performance of an MPEG2 encoder program.

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Large Matrix Multiplication on a Novel Heterogeneous Parallel DSP Architecture

Sohl

Wang

Liu

2009

Lecture Notes in Computer Science

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Performance Evaluation of an SIMD Architecture with a Multi-bank Vector Memory Unit

Cited by 5 publications

References 12 publications

Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices

Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices

Efficient vectorization of SIMD programs with non-aligned and irregular data access hardware

Large Matrix Multiplication on a Novel Heterogeneous Parallel DSP Architecture

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