Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices

Abstract

Endpoint devices for Internet-of-Things not only need to work under extremely tight power envelope of a few milliwatts, but also need to be flexible in their computing capabilities, from a few kOPS to GOPS. Near-threshold (NT) operation can achieve higher energy efficiency, and the performance scalability can be gained through parallelism. In this paper we describe the design of an opensource RISC-V processor core specifically designed for NT operation in tightly coupled multi-core clusters. We introduce instructionextensions and microarchitectural optimizations to increase the computational density and to minimize the pressure towards the shared memory hierarchy. For typical data-intensive sensor processing workloads the proposed core is on average 3.5× faster and 3.2× more energy-efficient, thanks to a smart L0 buffer to reduce cache access contentions and support for compressed instructions. SIMD extensions, such as dot-products, and a built-in L0 storage further reduce the shared memory accesses by 8× reducing contentions by 3.2×. With four NT-optimized cores, the cluster is operational from 0.6 V to 1.2 V achieving a peak efficiency of 67 MOPS/mW in a low-cost 65 nm bulk CMOS technology. In a low power 28 nm FDSOI process a peak efficiency of 193 MOPS/mW (40 MHz, 1 mW) can be achieved.Index Terms-Internet-of-Things, Ultra-low-power, Multi-core, RISC-V, ISA-extensions.

Stream Semantic Registers: A Lightweight RISC-V ISA Extension Achieving Full Compute Utilization in Single-Issue Cores

“…We present the necessary architectural changes in an existing multi-core platform (Section 2). 2) Competitive experimental results for the proposed architecture applied to a low power multi-core system [4]. We provide a performance, power, and area analysis for an implementation in a 22 nm technology and compare against other systems (Section 4).…”

“…The fundamental SSR usage follows the simple sequence outlined in Figure 4: address pattern configuration (1), enabling the stream semantics (2), computation (3), and disabling the stream semantics again (4). The configuration registers of the data mover are memory mapped and can be accessed by the processor via load and store instructions.…”

“…The processor loads two values from memory (flw), then multiplies them and accumulates the result (fmadd.s). We assume that iteration and pointer adjustment are performed via hardware loops and post-load increment, respectively, which are quite affordable microarchitectural enhancements [4]. In a single-issue core this takes at least three cycles to execute.…”

0.45 v and 18 μA/MHz MCU SOC with Advanced Adaptive Dynamic Voltage Control (ADVC)

“…With advances in Internet of Thing (IoT) applications and the expansion of mobile devices, energy consumption has become a primary focus of attention in integrated circuits design [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18]. While IoT applications cover a broad range of products from wearable devices, smart houses, automotive devices, smart meters to inspection tools and many others, more than 50% of the market is dominated by battery operated devices.…”

PAGURUS: Low-Overhead Dynamic Information Flow Tracking on Loosely Coupled Accelerators

“…(1) we present PAGURUS, a flexible methodology to design a low-overhead DIFT shell that secures loosely coupled accelerators; a shell is a hardware circuit whose design is independent from the design of the accelerators, thus simplifying the integration of DIFT in heterogeneous SoCs; we analyze the performance and cost overhead of the shell by synthesizing and running it on FPGAs: the shell has a low impact on execution time and area of the accelerators; (2) we define the metric of information leakage for accelerators to quantitatively measure the security of the DIFT shell: we show that, for any given accelerator, it is possible to find the minimum number of tags (required by DIFT) so that no information leakage is possible; we also show that few tags interleaved in the accelerators data are often sufficient to guarantee the absence of information leakage; arXiv:1912.11153v1 [cs.CR] 18 Dec 2019 (3) we perform a design-space exploration where we consider performance, cost and information leakage as optimization goals for the accelerators design: this study shows how to strengthen the security of hardware-accelerated applications in exchange of lower performance and higher cost; (4) we present a case study where the DIFT shell has been used to protect an accelerator integrated on a embedded SoC [31] we extended with DIFT: this shows why a holistic DIFT approach is necessary for heterogeneous SoCs.…”