Performance evaluation of CMOS low drop-out voltage regulators

Tantawy, Ramy; Brauer, E.J.

doi:10.1109/mwscas.2004.1353917

Cited by 32 publications

(12 citation statements)

References 2 publications

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“…Since the OTA is operating in these two potentials, the input terminals must be provided Error amplifier in the negative feedback condition decides the output voltage (V out ) by comparing error signal constantly with V ref that is 0.65V. According to Equation (9), to get the desired V out =4.5V, R f1 =14.8 kΩ, and R f2 =2.5 kΩ are chosen.…”

Section: A Design Of the Error Amplifier In The Proposed Ldo Regulatormentioning

confidence: 99%

Low Drop-Out Voltage Regulator as a Candidate Topology for Photovoltaic Solar Facilities

García

2024

RE&PQJ

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Abstract. This article aims to present the design of a 4.5-V, 450-mA low drop-out (LDO) voltage linear regulator based on a two-stage cascoded operational transconductance amplifier (OTA) as error amplifier for photovoltaic solar DC-DC regulation. The aforementioned two-stage OTA is designed with cascoded current mirroring technique to boost up the output impedance. The proposed OTA has a DC gain of 101 dB under no load condition.The designed reference voltage included in the LDO regulator is provided by a band gap reference with the temperature coefficient (T γ ) of 0.025 mV/ºC. The proposed LDO regulator has a maximum drop-out voltage of 0.5 V @ 450 mA of load current, and has the worst case power supply rejection ratio (PSRR) of [54.5 dB, 34.3 dB] @ [100 Hz, 10 kHz] in full load condition. All the proposed circuits are designed using a 0.35 µm CMOS technology. The design is checked in order to corroborate its performance for wide range of input voltage, founding that the circuit design works fine meeting all the initial specification requirements. Key wordsPhotovoltaic solar DC-DC regulator, low drop-out (LDO) voltage linear regulator, operational transconductance amplifier (OTA), band gap reference, cascoded current mirror.

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Section: A Design Of the Error Amplifier In The Proposed Ldo Regulatormentioning

confidence: 99%

Low Drop-Out Voltage Regulator as a Candidate Topology for Photovoltaic Solar Facilities

García

2024

RE&PQJ

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“…The proposed LDO regulator circuit (Fig. 5) was simulated to obtain its most important characteristics and parameters [9] like DC response and line regulation, load regulation, PSRR, open loop AC Response, response for load variations, settling time for load variations, and transient responses for input variations. On the one hand, DC response of the LDO circuit is obtained for the different loading conditions R L =10 Ω, 45 Ω and ∞.…”

Section: B Ldo Voltage Regulatormentioning

confidence: 99%

Design of a 4.5-V, 450-mA low-dropout voltage linear regulator based on a cascoded OTA

García

Grau

Bolea

2013

IECON 2013 - 39th Annual Conference of the IEEE Industrial Electronics Society

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“…As can be seen, references [12] and [6] require an external capacitor for its proper operation, whereas the proposed regulator does not require any external component to guarantee its stable operation. Furthermore, while reference [2] only works for slot-time operation, this work is able to produce constant output voltage for continuous operation.…”

Section: Comparison With Existing Workmentioning

confidence: 99%

“…2. Section 3 describes the simulation results in terms of the dropout voltage, line regulation, load regulation, quiescent current, power supply rejection ratio, stability, and silicon area [12]. A comparison with previously reported results is also provided.…”

Section: Introductionmentioning

confidence: 99%

Fully on-chip switched capacitor NMOS low dropout voltage regulator

Camacho

Gui

Moreira

2009

Analog Integr Circ Sig Process

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This paper presents a 1.5 V 50 mA low dropout voltage (LDO) regulator using an NMOS transistor as the output pass element. Continuous time operation of the LDO is achieved using a new switched floating capacitor scheme that raises the gate voltage of the pass element. The regulator has a 0.2 V dropout at a 50 mA load and is stable for a wide load current range with loading capacitances up to 50 pF. The output variation when a full load step is applied is 300 mV and the recovery time is below 0.3 ls. It is designed in a 0.13 lm CMOS process with an area of 0.008 mm 2 and its operation does not require any external component.

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Performance evaluation of CMOS low drop-out voltage regulators

Cited by 32 publications

References 2 publications

Low Drop-Out Voltage Regulator as a Candidate Topology for Photovoltaic Solar Facilities

Low Drop-Out Voltage Regulator as a Candidate Topology for Photovoltaic Solar Facilities

Design of a 4.5-V, 450-mA low-dropout voltage linear regulator based on a cascoded OTA

Fully on-chip switched capacitor NMOS low dropout voltage regulator

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