Performance evaluation of exclusive cache hierarchies

Zheng, Ying; Davis, Brian; Jordan, M.

doi:10.1109/ispass.2004.1291359

Cited by 29 publications

(1 citation statement)

References 4 publications

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“…The LLC, with a capacity of 64 MB, is used as a shared and a 32-way set associative cache. We also assumed and modeled the two-level caches integrated in processors to be exclusive and the relationship between the two-level caches and the LLC to be inclusive [18]. As Al-Zoubi et al [19] revealed no common wisdom about the best algorithm to use as a replacement policy for the caches of the three models, we use a pseudo least recently used (PLRU) algorithm, one of the options among the various algorithms for cache block replacement.…”

Section: Modeling and Workloadsmentioning

confidence: 99%

Cache memory organization for processing in memory

Kim

Moon

Kim

et al. 2019

IEICE Electron. Express

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A promising solution for assuring ultra-low latency in dataintensive application processing systems is processing in memory (PIM). Although most studies that have examined PIM-based computing systems have used cache memory, few have adequately explored a reasonable cache management policy for PIM. Therefore, this paper studies cache management policies for PIM-based computing systems and classifies existing PIM policies according to where they are located and how they are managed. To evaluate the policies, we model three types of PIM-based computing systems used in an in-memory system architecture. One model employs an internal-single cache, another an external cache hierarchy, and the other internal multiple cache-based PIM. We also simulate the performance and power consumption of the three models by their workloads, each with diverse characteristics. The experimental results show how cache policies influence the performance and power of PIM-based inmemory computing systems.

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Section: Modeling and Workloadsmentioning

confidence: 99%