Performance evaluation of noise coupling on Germanium based TSV filled material for future IC integration technique

Vadthiya

2021

Preprint

In this paper we have performed scaling performance of asymmetric junctionless (JL) SOI nanowire FET at 10 nm gate length (LG). To study the device electrical performance various DC metrics like SS, DIBL, ION/IOFF ratio are performed. Even at 5 nm, the device has good electrical properties with subthreshold swing (SS) = 64 mV/dec, drain induced barrier lowering (DIBL) = 45 mV/V, and switching ratio (ION/IOFF) = 106 shows a higher level of electrostatic integrity. Moreover, to study scaling flexibility towards analog/RF applications various parameters like transconductance (I), transconductance generation factor (TGF), total gate capacitance (Cgg), and cutoff frequency (fT) are determined. Furthermore, the dynamic power (DP) and static power (SP) consumption of the device with scaling is also presented. The findings of the study show that asymmetric JL nanowire FET is one of the scaling possibilities.

Section: Results Analysismentioning

confidence: 99%

Junctionless Gate-All-Around Nanowire FET with Asymmetric Spacer for Continued Scaling

Vadthiya

2021

Preprint

“…To overcome the limitations faced by merely shrinking devices, various new architectures have been proposed to continue scaling like SOI MOSFET, double gate MOSFET, tri-gate, step FinFET, and gate all around (GAA) MOSFET. [1][2][3][4][5][6][7][8][9][10] Since 2011, FinFET has emerged as a 3D device chip manufacturer for mass production in electronic industry. 11 Many approaches to enhance the device performance for sub-micron technology have been made, such as channel, gate, doping, and strain engineering techniques.…”

Section: Introductionmentioning

confidence: 99%

“…Scaling decreases the ON current ( I ON ) due to various SCEs and leads to performance degradations. To overcome the limitations faced by merely shrinking devices, various new architectures have been proposed to continue scaling like SOI MOSFET, double gate MOSFET, tri‐gate, step FinFET, and gate all around (GAA) MOSFET 1–10 . Since 2011, FinFET has emerged as a 3D device chip manufacturer for mass production in electronic industry 11 .…”

Section: Introductionmentioning

confidence: 99%

Design insights into RF /analog and linearity/distortion of spacer engineered multi‐fin SOI FET for terahertz applications

Int J RF Mic Comp-Aid Eng

Narendar

2021

Multi-fin devices are the most reliable option for terahertz (THz) frequency applications at nano-regime. In this work impact of spacer engineering on multi-fin SOI FET performance is evaluated by invoking single low-k (Air), high-k (Si 3 N 4 , HfO 2 ), and hybrid dual-k (Air + Si 3 N 4 ) spacer in the underlap section at nano-regime. The simulation study reveals that the high-k (HfO 2 ) spacer gives a higher switching ratio (I ON /I OFF ) in the order of ~10 7 , subthreshold swing (SS) = 72 mV/dec, drain induced barrier lowering (DIBL) = 22.14 mV/V and quality factor (Q) = g m /SS = 0.16 μS-dec/mV. Furthermore, to measure the suitability of the device for high frequency applications various analog/RF parameters are studied. The high-k (HfO 2 ) spacer dominates DC and analog performance, whereas the low-k (Air) spacer dominates the RF domain with f T = 1.26 THz, GBW = 0.251 THz, TFP = 29 THz range, and with smaller intrinsic delays. Hybrid dual-k spacer (Air + Si 3 N 4 ) outperforms in terms of gain (A V ) and output resistance (R o ). The Air spacer exhibits lower dynamic power of 2.09 aJ/μm and power consumption of 1.04 aJ/μm. The linearity metrics for multi-fin SOI FET parameters like g m2 , g m3 , HD1, HD2, THD, and VIP2 are also studied. The Air spacer followed by hybrid spacer outperforms in linearity, and harmonic distortion components and ensures its potential for RF applications at nano-regime.

“…However, with SiO2, Si3N4, HfO2 spacers the device exhibits IOFF lesser than nA which is feasible for scaling towards low power applications. The mathematical form of SS and DIBL is given as follows [13,14]: TGF is an important metric in determining the power required to obtain high speed with respect to gate bias.…”

Section: Introductionmentioning

confidence: 99%

Asymmetric Spacer Junctionless GAA Nanowire FET for Continued Scaling

Narendar

2021

Preprint

We demonstrate junctionless (JL) n-channel SOI nanowire FET with asymmetric spacer at nano regime. The impact of various spacer dielectrics on device performance is presented and various electrical characteristics are analyzed. The gate length (LG) scaling impact of the asymmetric spacer with various spacers on ION, IOFF, and ION/IOFF is analyzed. The device exhibits excellent electrical characteristics with SS = 64 mV/dec, DIBL = 45 mV/V, ION/IOFF = 106 even at 5 nm LG ensures better electrostatic integrity. From the result analysis it is noted that spacer plays a detrimental role in reducing OFF current (IOFF) at lower LG. Moreover, the power analysis on scaling with various spacer dielectrics is performed. The analog/RF performance is also performed and scaling feasibility with HfO2 spacer is presented. The result analysis ensures asymmetric JL nanowire FET is one of the possible options to continue scaling.