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The most affected disease in recent years is Severe Acute Respiratory Syndrome Coronavirus 2 (SARS-COV-2) that is notable as COVID-19. It has been started as a disease in one place and arisen as a pandemic throughout the world. A serious health problem is developed in the lungs due to the effect of this coronavirus. Sometimes it may result in death as a consequence of extensive alveolar damage and progressive respiratory failure. Hence, early detection and appropriate diagnosis of corona virus in patient’s body is very essential to save the lives of affected patients This work evolves a Silicon (Si) based label-free electrical device i.e. the reduced graphene oxide field-effect transistor (rGO FET) for SARS-CoV-2 detection. Firstly rGO FET functionalized with SARS-CoV-2 monoclonal antibodies (mAbs). Then the rGO FET characteristic response is observed to detect the antibody-antigen reaction of SARS-CoV-2 with different molar ranges. The developed GFET shows better performance towards the drain current and limit-of-detection (LoD) up to 2E-18 M. Therefore, we believe that an intense response was observed than the earlier developed devices and signifies impressive capability for subsequent implementation in point-of-care (PoC) diagnostic tests.

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Demand for accommodating more and new functionalities within a single chip such as SOC needs a novel devices and architecture such as FinFET device instead of MOSFET. FinFET is emerged as nonplanar, multigate device to overcome short channel effects such as subthreshold swing deterioration, drain induced barrier lowering, threshold voltage roll off which degrade circuit performance. As the need of device technology is mounting in electronic gadgets the important parameters are taken into consideration such as low leakage, high reliability, low power dissipation, and high operating speed.Reliability is one of key considerations in converting a proof of concept into reality. In this work Reliability of FinFET device is studied experimentally according to ITRS (international technology roadmap for semiconductor) roadmap using several standard test protocols such as multiple current stressing, harsher environment conditions, and effect of electromigration. Furthermore, power analysis of FinFET based SRAM is done by using 7nm bsimcmg PTM les in mentor graphics tool. The FinFET based SRAM shown low leakage, power dissipation, delay compared to existing conventional MOSFET based SRAM.