Performance Evaluation of Probe-Send Fault-tolerant Network-on-chip Router

Mediratta, S.D.; Draper, J.

doi:10.1109/asap.2007.4429960

Cited by 10 publications

(5 citation statements)

References 5 publications

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“…For other cases (change in V and N), this characterization is not very significant because phit size is constant and the clock cycle is almost the same as that of the best-case router latency at the expense of increase in area and power. The effect of increasing V is more dynamic because of its interference with the blocking probability, and is reported in a separate paper [10]. Bandwidth increases linearly with increments in the phit size, and the bestcase router latency remains almost the same.…”

Section: Figure 6 Characterization Wrt Number Of Nodesmentioning

confidence: 86%

Characterization of a Fault-tolerant NoC Router

Mediratta¹,

Draper²

2007

2007 IEEE International Symposium on Circuits and Systems (ISCAS)

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Abstract-With increasing reliability concerns for current and next generation VLSI technologies, fault-tolerance is fast becoming an integral part of system-on-chip (SoC) and multicore architectures. Another concern for these architectures is increasing global wire lengths with associated issues leading to network-on-chips (NoC) becoming standard for on-chip global communication. We recognize these issues and present an onchip generic fault-tolerant routing algorithm. The microarchitecture of a NoC router implementing the proposed routing algorithm for a k-ary 2-cube topology is provided. The proposed router works in two phases. In the first phase, the network is explored for an existing path between sourcedestination pairs after reset or during system reconfiguration after fault detection. Existing paths are cached and used in the second phase of data communication during normal system operation. The presented router architecture also proposes a concept of dynamic multiplexing of virtual channels on physical channels to efficiently utilize physical channel bandwidth. The above approaches complement each other and when combined together, result in an efficiently realizable high-performance NoC fault-tolerant router. An implementation characterization of this k-ary 2-cube torus router in terms of area, power and critical path delay in IBM Cu-08 technology is presented, along with bandwidth and latency characterization for relevant cases.

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Section: Figure 6 Characterization Wrt Number Of Nodesmentioning

confidence: 86%

Characterization of a Fault-tolerant NoC Router

Mediratta¹,

Draper²

2007

2007 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…Works on [15], [16], [17], [18] propose network exploration techniques to detect permanent faults. Some of them could be implemented only on regular topologies, while others are more flexible.…”

Section: B Fault Tolerace At Routing Levelmentioning

confidence: 99%

“…Such routing method requires a large memory on every router to store all complete paths, and the paths computation after a fault be detected, be done on a central (not faulty) node in order to avoid deadlock situations on new routing scheme. Other described mechanisms in this document uses distributed routing, instead of centralized control which needs a completely knowledge of the full network Works on [15] and [17] propose an adaptive routing mechanism based on paths exploration using up to 8 virtual channels for supporting permanent faults on k.-ary 2-cube NoCs.…”

Section: B Fault Tolerace At Routing Levelmentioning

confidence: 99%

Fault Tolerance on NoCs

Montañana

Andrés²,

Tirado

2013

2013 27th International Conference on Advanced Information Networking and Applications Workshops

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Multi-Processor Systems-on-Chip (MPSoCs) are increasingly popular in embedded systems, but also on high performance systems. In such systems, the data bandwidth requirements keeps increasing as the number of processing elements increases. Therefore, a Network-on-Chip (NoCs) communication architecture use to be preferred than a communication based on shared buses, because it provides higher communication performance.The probability of failure increases in this systems, due to these great advances in integration scales and the increasing number of components on chip. Therefore Fault Tolerance will become a key aspect on designing the near future VLSI SoC, and especially on their interconnection Network on Chip (NoC). This paper focuses on describe the particular aspects of NoCs, and the proposed fault-tolerant strategies for NoCs.

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“…Another trend for such architectures is network-on-chip (NoC) becoming a standard for on-chip global communication. In an earlier work, a generic fault tolerant routing algorithm in the context of NoCs has been presented [5], [6].In this paper, we characterize the system requirements of NoC based systems and propose a novel routing protocol for providing additional Bandwidth with QoS in NoCs.…”

Section: Introductionmentioning

confidence: 99%

Improvement network-on-chip bandwidth utilization through multi protocol label switching by dividing bandwidth

Rad

Kourdy

Pooyan

et al. 2010

2010 the 2nd International Conference on Computer and Automation Engineering (ICCAE)

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we propose a combination of Mesh topology and Bisection routing in MPLS and IP network-on-chip which can increase Communication load with quality of service which is suitable for multimedia applications. We compare the performance of 2d-Mesh architectures in the sense of on chip network design methodology. The simulations of the architectures are done with two-dimensional Mesh topologies that used MPLS base recovery mechanism with bisection routing in source switch, to provide additional bandwidth for application that need more bandwidth than one link. We also carry out the high level simulation of on chip network using NS-2 to verify the analytical analysis.

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Performance Evaluation of Probe-Send Fault-tolerant Network-on-chip Router

Abstract: Abstract

Cited by 10 publications

References 5 publications

Characterization of a Fault-tolerant NoC Router

Characterization of a Fault-tolerant NoC Router

Fault Tolerance on NoCs

Improvement network-on-chip bandwidth utilization through multi protocol label switching by dividing bandwidth

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