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Abstract-With increasing reliability concerns for current and next generation VLSI technologies, fault-tolerance is fast becoming an integral part of system-on-chip (SoC) and multicore architectures. Another concern for these architectures is increasing global wire lengths with associated issues leading to network-on-chips (NoC) becoming standard for on-chip global communication. We recognize these issues and present an onchip generic fault-tolerant routing algorithm. The microarchitecture of a NoC router implementing the proposed routing algorithm for a k-ary 2-cube topology is provided. The proposed router works in two phases. In the first phase, the network is explored for an existing path between sourcedestination pairs after reset or during system reconfiguration after fault detection. Existing paths are cached and used in the second phase of data communication during normal system operation. The presented router architecture also proposes a concept of dynamic multiplexing of virtual channels on physical channels to efficiently utilize physical channel bandwidth. The above approaches complement each other and when combined together, result in an efficiently realizable high-performance NoC fault-tolerant router. An implementation characterization of this k-ary 2-cube torus router in terms of area, power and critical path delay in IBM Cu-08 technology is presented, along with bandwidth and latency characterization for relevant cases.

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This paper describes the implementation of theexception handling mechanism in the second prototype version of the Data-Intensive Architecture (DIVA) processing-inmemory (PIM) chip. This implementation features architectural simplicity, low area (54289 p 2 ) , delay (2.643 nanosecond) and power consumption (7.6 milliwatts), and effective hardware support for complex cases of exception handling. This work provides a description of handling memory-access, execution and communication-related exceptions in an area-and powerefficient manner, which are key design specifications for DIVA.The current implementation has been tested by verifying various exceptions on DIVA-I1 PIM chips running at 140MHz in the memory system of a HP Itanium2-based Long's Peak server. The generic nature of the DIVA exceptions and their classification makes the current implementation suitable and easy for use in diverse microarchitectures with little modification.