Performance Evaluation of Spacer Dielectric Engineered Vertically Stacked Junctionless Nanosheet FET for Sub-5 nm Technology Node

This article for the first time reports the design and performance optimization of Junctionless (JL) Bottom spacer (BSP) FinFET. Initially to get the desired value of workfunction (∅_m) and fin thickness (Tfin) for analog/RF analysis, the optimization of these parameters has been done by considering several values. It has been noticed that the increase in ∅_m and reduction in Tfin can lead to better electrical performance with suppressed short channel effects (SCE). Further, it is also observed that reduction in bottom spacer height (HBSP) can fetch enhanced analog/RF performance considering the improvement noticed in transconductance (gm), intrinsic gain (AV), transconductance generation factor (TGF), cutoff frequency (fT), and Gain frequency product (GFP). Moreover, when the bottom spacer dielectric permittivity (KBSP) is increased from 3.9 to 22, it has been found that the analog/RF performance degrades significantly.

Section: Optimization Of Bottom Spacer Height (H Bsp ) Of Jl-bspmentioning

confidence: 63%

Design and Performance Optimization of Junctionless Bottom Spacer FinFET for Digital/Analog/RF Applications at Sub-5nm Technology Node

Valasa¹,

Kotha²,

Narendar³

et al. 2023

“…35 is also decreased for TiO 2 spacer due to the significance increase in C gd in comparison with g ds improvement. The Gain Frequency Product 36 is an analog FOM that is used to evaluate the performance of a device. It is observed that the pronounced superiority of TiO 2 in terms of its lower f t leads to a reduction in GFP when compared to other spacers.…”

Section: Simulation Resultsmentioning

confidence: 99%

Optimization of Sidewall Spacer Engineering at Sub-5 nm Technology Node For JL-Nanowire FET: Digital/Analog/RF/Circuit Perspective

Anguru,

Aryasomayajula,

Kotha

et al. 2024

Self Cite

This paper presents a performance analysis of 3-stack JL-NWFETs with different spacer materials and spacer lengths. The DC and analog/RF performance is analysed at the device level, and circuit level. In single-k spacer analysis, TiO2 exhibits lowest IOFF of ~89.28%, and largest ION/IOFF ratio with better subthreshold performance of ~42.51% as compared to Air spacer at Lext= 7nm. In addition, TiO2 spacer is suitable for analog applications while Air spacer for RF applications. The dual-k spacer analysis is also performed and the TiO2+Air spacer showed prodigious DC/Analog/RF performances dominating all other combinations. Further investigations into inner high-k spacer analysis (Lsp,hk) revealed that higher Lsp,hk is suitable for DC and Analog applications whereas lower Lsp,hk for RF applications. The CS amplifier designed for configurations of Lsp,hk showed better gain for higher Lsp,hk with the amplification gain of ~4.8V/V. Overall, this analysis serves as a beacon, guiding the future of JL-NWFET design for spellbinding nano-electronic devices at sub-5nm technology node.

“…Introduction of spacer reduces DIBL due to shift of lateral field from gate edge towards drain, so source gets screened. 26 Comparison of analog parameters for D1 to D6.-In this subsection, the effect of analog parameters such as transconductance (g m ), output conductance (g d ), early voltage (V EA ), transconductance generation factor (TGF), and intrinsic gain (A V ) are compared for different device designs D1 to D6.…”

Section: Resultsmentioning

confidence: 99%

Performance Investigation of FinFET Structures: Unleashing Multi-Gate Control through Design and Simulation at the 7 nm Technology Node for Next-Generation Electronic Devices

Valasa,

Ramakrishna,

Bhukya

et al. 2023

Self Cite

We outline a original study that represents the first investigation of its kind, focusing on DC and analog/RF performance of structural flavors of FinFET. A total of six structural variations (D1 to D6 devices) in FinFET as per the IRDS 7 nm technology node specifications is explored. Through extensive simulations, our findings demonstrate that the incorporation of gate stack, spacer, and source/drain extension concepts in FinFETs leads to superior performance. The DC performance analysis produced near-ideal SS (~65mV/dec) performance, lower leakage currents, improved switching performance, and reduced DIBL values for D3 to D6 devices owing to the incorporation of gate stack, spacer integration, and source/drain extension doping. In terms of analog/RF performance, the best suitable device is found to be D4 device having designed with 1017 cm-3 n-type lightly-doped source/drain regions, spacer, and gate stack integrations. A significant improvement such as higher gm, reduced gd, enhanced AV, improved fT, GFP, GTFP, and TFP are obtained for D4 device marking a breakthrough in the FinFET designing. Overall, the findings contribute to the advancement of FinFET at 7 nm technology node, opening up new opportunities for applications in various electronic systems demanding improved device performance.