Performance Fluctuation of FinFETs With Schottky Barrier Source/Drain

Abstract

A considerable performance fluctuation of FinFETs featuring PtSi-based Schottky barrier source/drain is found. The Fin-channels measure 27-nm tall and 35-nm wide. Investigation of similarly processed transistors of broad gate-widths reveals a large variation in the position of the PtSi/Si interface with reference to the gate edge along the gate width. This variation suggests an uneven underlap between the PtSi and the gate from device to device for the FinFETs, since essentially only one silicide grain would be in contact with each Fin-channel at the PtSi/Si interface. The size of the underlap is expected to sensitively affect the performance of the FinFETs. Index Terms-FinFETs, gate underlap, MOSFETs, platinum silicide PtSi, Schottky barrier source/drain (SB-S/D), transmission electron microscopy (TEM).

Small-signal analysis of high-performance p- and n-type SOI SB-MOSFETs with dopant segregation

“…A statistical analysis takes into account any device fluctuations, e.g. variations of the underlap between the gate stack and the silicide contact [11] as well as inhomogeneities of the oxide and silicon thickness [12]. Fig.…”

Low-frequency noise in FinFETs with PtSi Schottky-barrier source/drain contacts

“…1., revealed a variation in drain current (I D ) and subthreshold behavior across different dies and also a slight asymmetry as source and drain were interchanged. From previous analysis the variation could be related to the actual position of the PtSi to the channel interface [6]. It can also be observed that devices with a lower on-current have a slightly more pronounced ambipolar behavior, indicating higher hole barrier and lower electron barrier.…”

Systematic study of Schottky barrier MOSFETs with dopant segregation on thin-body SOI

“…The statistical analysis of 230-250 devices of each kind of transistor takes into account any device fluctuations, e.g. substantial variations of the overlap between the gate stack and the silicide contact [11] as well as inhomogeneities of the oxide and silicon thickness [16]. pected for an SB-MOSFET, the device exhibits an ambipolar switching behaviour with almost equal on-currents in the n-type branch ðV gs À V t > 0Þ and in the p-type branch ðV gs À V t < 0Þ.…”

“…Another very promising technique is the combination of silicides like PtSi or the midgap material NiSi with dopant segregation (DS). Different approaches with implantation to silicide (ITS) followed by a drive in anneal [10,11], implantation to metal (ITM) [10] and the silicidation induced dopant segregation [1,2] have been reported. In all cases dopants pile-up at the silicide/silicon interface during DS and form a thin highly doped layer which causes a strong up-or downward band bending depending on the type of dopants.…”