Performance Metrics and Models for Shared Cache

Ding, Chen; Xiang, Xiaoya; Bao, Bin; Luo, Hao; Luo, Yingwei; Wang, Xiaolin

doi:10.1007/s11390-014-1460-7

Cited by 15 publications

(7 citation statements)

References 125 publications

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“…On modern multicore processors, the cache is shared at one or more levels. Ding et al (2014) defines composability, which means that the locality of a co-run can be computed from the locality of solo runs. The reuse interval is composable between independent programs if they are uniformly interleaved.…”

Section: Composability and Cache Sharingmentioning

confidence: 99%

A Relational Theory of Locality

Yuan

Ding

Smith

et al. 2019

ACM Trans. Archit. Code Optim.

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In many areas of program and system analysis and optimization, locality is a common concept and has been defined and measured in many ways. This article aims to formally establish relations between these previously disparate types of locality. It categorizes locality definitions in three groups and shows whether and how they can be interconverted. For the footprint, a recent metric, it gives a new measurement algorithm that is asymptotically more time/space efficient than previous approaches. Using the conversion relations, the new algorithm derives with the same efficiency different locality metrics developed and used in program analysis, memory management, and cache design.

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Section: Composability and Cache Sharingmentioning

confidence: 99%

A Relational Theory of Locality

Yuan

Ding

Smith

et al. 2019

ACM Trans. Archit. Code Optim.

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“…Similar to Jiang's work, the model requires upstream cache simulations to obtain the inputs. Moreover, Chen Ding et al [15] proposed a footprint theory based on the concept of the memory footprint. The theory also deals with the properties of footprint composition and proposes optimal co-scheduling by using shared footprint metric.…”

Section: Related Workmentioning

confidence: 99%

Analytical Modeling the Multi-Core Shared Cache Behavior With Considerations of Data-Sharing and Coherence

Ling

Wang

et al. 2021

IEEE Access

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To mitigate the ever worsening "Power wall" and "Memory wall" problems, multi-core architectures with multilevel cache hierarchies have been widely used in modern processors. However, the complexity of the architectures makes the modeling of shared caches extremely complex. In this paper, we propose a data-sharing aware analytical model for estimating the miss rates of the downstream shared cache in a multi-core environment. Moreover, the proposed model can also be integrated with upstream cache analytical models with the consideration of multi-core private cache coherent effects. The integration avoids time-consuming full simulations of the cache architecture, which are required by conventional approaches. We validate our analytical model against gem5 simulation results under 13 applications from PARSEC 2.1 benchmark suites. We compare the L2 cache miss rates with the results from gem5 under 8 hardware configurations including dual-core and quad-core architectures. The average absolute error is less than 2% for all configurations. After integrated with the upstream model, the overall average absolute error is 8.03% in 4 hardware configurations. As an application case of the integrated model, we also evaluate the miss rates of 57 different cache configurations in multi-core and multi-level cache scenarios.

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“…The proof of composition invariance is straightforward with rearrangement of the terms in Equations (10), (12), and (13). It relies on the mathematical property of VFP operations: the differentiation is distributive over the addition.…”

Section: Sharing Exclusive Llcmentioning

confidence: 99%

“…Beckmann and Sanchez [2] observed that the access to shared cache by a program is effectively random due to the filtering by private cache. Models of cache have been developed with different assumptions of randomness ( [2,3,20,44,54] as discussed in Ding et al [13]). Our results suggest such effect but no obvious solution: even partition works well, but proportional partitioning does not.…”

Section: Theory Versus Heuristicsmentioning

confidence: 99%

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Cache Exclusivity and Sharing

Ding

Luo

et al. 2017

ACM Trans. Archit. Code Optim.

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A problem on multicore systems is cache sharing, where the cache occupancy of a program depends on the cache usage of peer programs. Exclusive cache hierarchy as used on AMD processors is an effective solution to allow processor cores to have a large private cache while still benefitting from shared cache. The shared cache stores the "victims" (i.e., data evicted from private caches). The performance depends on how victims of co-run programs interact in shared cache.This article presents a new metric called the victim footprint (VFP). It is measured once per program in its solo execution and can then be combined to compute the performance of any exclusive cache hierarchy, replacing parallel testing with theoretical analysis. The work evaluates the VFP by using it to analyze cache sharing by parallel mixes of sequential programs, comparing the accuracy of the theory to hardware counter results, and measuring the benefit of exclusivity-aware analysis and optimization.

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Performance Metrics and Models for Shared Cache

Cited by 15 publications

References 125 publications

A Relational Theory of Locality

A Relational Theory of Locality

Analytical Modeling the Multi-Core Shared Cache Behavior With Considerations of Data-Sharing and Coherence

Cache Exclusivity and Sharing

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