Performance Monitoring on the POWER5™ Microprocessor

Scheduling heterogeneous multi-cores through Performance Impact Estimation (PIE)

“…Collecting CPI stacks on out-of-order cores is more complicated because of various overlap effects between miss events, e.g., a longlatency load may hide the latency of another independent long-latency load miss or mispredicted branch, etc. Recent commercial processors such as IBM Power5 [23] and Intel Sandy Bridge [12] however provide support for computing memory stall components. PIE scheduling also requires the number of LLC misses and the number of dynamically executed instructions, which can be measured using existing hardware performance counters.…”

Dynamic performance tuning for speculative threads

“…For cores with multiple commit width, at each cycle, multiple counters can increase, each corresponding to a retirement slot. The mechanism described here is similar to the performance monitors in IBM POWER5 [32]; with the following extensions: depending on how the cache miss is served, the dCache is incremented differently. Details will be discussed in Section 4.1.1.…”

“…Obtaining accurate execution time breakdowns in an out-of-order processor core is difficult due to the overlap of multiple on-the-fly instructions. Examining the instructions at the head of ROB gives us some clues [32] to the cause of a stall. In this section, we show how to obtain such execution time breakdowns for TLS execution.…”

“…On the other hand, Lu et al [25,26] generate helper thread prefetches using information obtained from the hardware monitors on the Sun UltraSPARC R . The optimization framework proposed in ADORE [25,26] is similar to the speculative thread optimization framework proposed in this paper, with the following differences: (i) our work uses hardware-based performance counters that generate cycle breakdowns [9,32], while ADORE uses event-based hardware performance counters; (ii) in ADORE, a dynamic compiler is responsible for generating and patching re-optimized code at runtime, while our scheme does not require dynamic code generation; and (iii) we carefully evaluate the performance impact of speculation threads before optimization, while ADORE does not evaluate the effectiveness of the prefetching threads.…”

“…The profile can be obtained through either software instrumentation or hardware performance monitor sampling. In this paper, hardware-based performance counters [9,32] are used. A small piece of code that initializes these counters is executed at the beginning of execution by modifying a libc entry-point routine named libc start main.…”