Scheduling heterogeneous multi-cores through Performance Impact Estimation (PIE)

Craeynest, Kenzo Van; Jaleel, Aamer; Eeckhout, Lieven; Narváez, Paolo; Emer, Joel

doi:10.1145/2366231.2337184

Cited by 116 publications

(126 citation statements)

References 32 publications

Supporting

Mentioning

123

Contrasting

Unclassified

Order By: Relevance

“…To put the results for MONARCH in context to other approaches, we compared it to PIE [5], which predicts the performance of a running program on one core type using hardware performance counters from another core type. Because PIE was not designed for multithreaded programs, we extended it to aggregate performance across multiple threads.…”

Section: Comparison To Piementioning

confidence: 99%

“…One approach executes a program on all core types to measure relative performance for picking the type that achieves performance and power goals [2], [3]. Recent work uses analytic and experimental models [4], [5], [6], [7]. Performance Impact Estimation is a state-of-the-art analytic model to select core type [5].…”

mentioning

confidence: 99%

“…Recent work uses analytic and experimental models [4], [5], [6], [7]. Performance Impact Estimation is a state-of-the-art analytic model to select core type [5]. It uses performance counters gathered on one core type to predict program performance on another core type to choose between narrow in-order and wide out-of-order cores for single-threaded programs.…”

mentioning

confidence: 99%

“…For single-threaded programs, the mapping problem consists of selecting one parameter, core type, which has been the focus of past work [8], [9], [10], [5], [6], [2], [3]. To get the full promise of ACMPs, however, multithreaded programs must also be considered.…”

mentioning

confidence: 99%

“…Specifically, big cores are designed to extract instruction-level parallelism (ILP) and memory-level parallelism (MLP). For a thread to "run fast" on a big core, it needs both ILP and MLP-in fact, the thread may execute as fast on a small core as a big core, if it is memory-bound and lacks sufficient ILP to mask memory operations [5]. For a program with a large working set, a cluster of big cores with big cache might have better performance than a cluster with little cores and small cache.…”

mentioning

confidence: 99%

See 4 more Smart Citations

Performance Modeling of Multithreaded Programs for Mobile Asymmetric Chip Multiprocessors

Moore¹,

Childers

Xue

2015

2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium

View full text Add to dashboard Cite

Abstract-Asymmetric chip multiprocessors (ACMPs) have multiple core types that are instruction-set compatible but optimized differently to trade performance and power in mobile devices. The challenge for ACMPs is to map the program to the best core type and thread count to achieve performance requirements under power constraints. This paper describes an empirical strategy, MONARCH, to automatically build estimation models that capture how a multithreaded program's performance scales with thread count and core type. We show that MONARCH's models are accurate and useful to find mappings that achieve performance goals while minimizing power.

show abstract

Section: Comparison To Piementioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

See 3 more Smart Citations

Performance Modeling of Multithreaded Programs for Mobile Asymmetric Chip Multiprocessors

Moore¹,

Childers

Xue

2015

2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium

View full text Add to dashboard Cite

show abstract

An efficient model for quantifying the interaction between structural properties of software and hardware in the ARM big.LITTLE architecture

Stepanovic

Georgakarakos

Holmbacka

et al. 2019

Concurrency and Computation

View full text Add to dashboard Cite

Heterogeneous architectures offer the opportunity to achieve high performance and energy efficiency by selecting appropriate cores for the execution of ever-changing software applications. Appropriate core selection depends on the interaction between the structural properties of the software and the hardware that influences the performance of the software. We propose a model for efficient core selection when executing software on ARM's big.LITTLE heterogeneous architecture. It features a metric based on the correlation between the performance and the number of last-level data cache (LLC) misses on a big and a LITTLE core. Additionally, our model defines a soft threshold in terms of the number of LLC misses, which determines efficient core selection. We verify the model using stress and variable workload benchmarks as well as two popular high-throughput applications for mutlicore targets, namely, HEVC and LDPC decoders, profiled with X-Mem, Linux perf, and PMCTrack dynamic tools. Results show that our model can be used for efficient core selection with a relatively small error probability.

show abstract

Data Centers Job Scheduling with Deep Reinforcement Learning

Liang

Yang

Chen

2020

Advances in Knowledge Discovery and Data Mining

View full text Add to dashboard Cite

Efficient job scheduling on data centers under heterogeneous complexity is crucial but challenging since it involves the allocation of multi-dimensional resources over time and space. To adapt the complex computing environment in data centers, we proposed an innovative Advantage Actor-Critic (A2C) deep reinforcement learning based approach called A2cScheduler for job scheduling. A2cScheduler consists of two agents, one of which, dubbed the actor, is responsible for learning the scheduling policy automatically and the other one, the critic, reduces the estimation error. Unlike previous policy gradient approaches, A2cScheduler is designed to reduce the gradient estimation variance and to update parameters efficiently. We show that the A2cScheduler can achieve competitive scheduling performance using both simulated workloads and real data collected from an academic data center.

show abstract

Scheduling heterogeneous multi-cores through Performance Impact Estimation (PIE)

Abstract: Single-ISA heterogeneous multi-core processors are typically composed of small (e.g., in-order) power-efficient cores and big (e.g., out-of-order)

Cited by 116 publications

References 32 publications

Performance Modeling of Multithreaded Programs for Mobile Asymmetric Chip Multiprocessors

Performance Modeling of Multithreaded Programs for Mobile Asymmetric Chip Multiprocessors

An efficient model for quantifying the interaction between structural properties of software and hardware in the ARM big.LITTLE architecture

Data Centers Job Scheduling with Deep Reinforcement Learning

Contact Info

Product

Resources

About