Performance of a 650V SiC Diode with Reduced Chip Thickness

Rupp, Roland; Gerlach, R.; Kirchner, Uwe; Schlögl, A.; Kern, R.

doi:10.4028/www.scientific.net/msf.717-720.921

Cited by 25 publications

(19 citation statements)

References 2 publications

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“…Thinning the wafer is effective in cutting conduction losses. However, realization of a thin substrate needs major revisions in the process and procedures [33,34]. For example, back grinding and backside silicide formation are set later in the entire process because the number of thin wafer handling processes should be as low as possible.…”

Section: Further Challenges For Lower Lossesmentioning

confidence: 99%

Practical applications of SiC-MOSFETs and further developments

Furuhashi

Tomohisa

Kuroiwa

et al. 2016

Semicond. Sci. Technol.

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The next generation power modules using SiC-MOSFETs have been developed for over ten years. From our successful results, we have released SiC power modules which have been used in railway vehicles, industrial machines and home appliances, etc. Low on-resistance 3.3 kV SiC-MOSFETs have been realized by JFET doping and they demonstrated a loss reduction of 55% in a traction inverter compared to a conventional system. In the case of a 1.2 kV MOSFET, a 1 cm 2 die verified that it can control a large current of over 600 A. For home appliances, we reduce the trade-off between the threshold voltage and channel mobility by a new gate oxide process. High threshold voltage SiC-MOSFETs having a low onresistance contribute to the low cost installation of SiC-MOSFETs into air conditioners and achieved a loss reduction of 45% in DC converters. For further reduction of conduction loss, we investigated new structures and technologies. Trench SiC-MOSFETs having a bottom p-well verify lower on-resistance and a larger SCSOA than those of planar MOSFETs. The optimization of the dopant concentration in the drift layer and a reduction of wafer thickness verified the reduction of on-resistance. They are expected to contribute to a lower power loss.

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Section: Further Challenges For Lower Lossesmentioning

confidence: 99%

Practical applications of SiC-MOSFETs and further developments

Furuhashi

Tomohisa

Kuroiwa

et al. 2016

Semicond. Sci. Technol.

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“…Therefore, ultrathin wafers with excellent performance are of remarkable significance for high-power and extreme working conditions. Generally, the wafer back-thinning process for SiC wafer involves mechanical grinding using diamond abrasives, directly resulting in wafer fragmentations and deformations owing to the formation of microcracks [13,14].…”

Section: Introductionmentioning

confidence: 99%

Understanding the Mechanisms of SiC–Water Reaction during Nanoscale Scratching without Chemical Reagents

Cheng

Luo

Lu³

et al. 2022

Micromachines

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Microcracks inevitably appear on the SiC wafer surface during conventional thinning. It is generally believed that the damage-free surfaces obtained during chemical reactions are an effective means of inhibiting and eliminating microcracks. In our previous study, we found that SiC reacted with water (SiC–water reaction) to obtain a smooth surface. In this study, we analyzed the interfacial interaction mechanisms between a 4H-SiC wafer surface (0001¯) and diamond indenter during nanoscale scratching using distilled water and without using an acid–base etching solution. To this end, experiments and ReaxFF reactive molecular dynamics simulations were performed. The results showed that amorphous SiO2 was generated on the SiC surface under the repeated mechanical action of the diamond abrasive indenter during the nanoscale scratching process. The SiC–water reaction was mainly dependent on the load and contact state when the removal size of SiC was controlled at the nanoscale and the removal mode was controlled at the plastic stage, which was not significantly affected by temperature and speed. Therefore, the reaction between water and SiC on the wafer surface could be controlled by effectively regulating the load, speed, and contact area. Microcracks can be avoided, and damage-free thinning of SiC wafers can be achieved by controlling the SiC–water reaction on the SiC wafer surface.

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“…However, the dominant commercially available SiC Schottky diodes integrate p-n junctions in parallel with metal-semiconductor junctions, known as merged PN-Schottky (MPS) diodes. An additional feature of modern SiC Schottky diodes is the use of thinned down SiC chips, achieved by backgrinding SiC wafers from the standard 350 μm to as low as 110 μm [2][3][4][5][6][7][8][9] . A primary motivation for thinning the wafer is to reduce the electrical resistance of the chip 3,6,8,9 , which in turn reduces the thermal resistance and enables better heat removal 2,4,5,7 .…”

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confidence: 99%

“…An additional feature of modern SiC Schottky diodes is the use of thinned down SiC chips, achieved by backgrinding SiC wafers from the standard 350 μm to as low as 110 μm [2][3][4][5][6][7][8][9] . A primary motivation for thinning the wafer is to reduce the electrical resistance of the chip 3,6,8,9 , which in turn reduces the thermal resistance and enables better heat removal 2,4,5,7 . The heat removal is important because the SiC chip temperature must be maintained within the specified operating limit, which is crucial for reliable operation during surge-current events.…”

mentioning

confidence: 99%

“…Research has been focused on providing an in-depth assessment on the acceleration of heat removal due to the lower thermal resistance in devices with thinner chips 2,4,5 . There are also statements, including ones by the manufacturers of commercial SiC Schottky diodes, that wafer thinning in conjunction with the MPS structure enhances the surge-current capability of the device 5,[7][8][9] . However, it has also been reported by manufacturers that there is a trade-off between decreasing the electrical resistance and decreasing the thermal capacitance 2 .…”

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The effect of wafer thinning and thermal capacitance on chip temperature of SiC Schottky diodes during surge currents

Damcevska,

Dimitrijev,

Haasmann

et al. 2023

Sci Rep

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Due to superior material properties of SiC for high-voltage devices, SiC Schottky diodes are used in energy-conversion systems such as solar-cell inverters, battery chargers, and power modules for electric cars and unmanned aerial vehicles. The reliable operation of these systems requires the chip temperature of SiC Schottky diodes to be maintained within the limit set by the device package. This is especially crucial during surge-current events that dissipate heat within the device. As a thermal-management method, manufactures of commercial SiC Schottky diodes have introduced wafer thinning practices to reduce the thickness of the SiC chip and, consequently, to reduce its thermal resistance. However, this also leads to a reduction in the thermal capacitance. In this paper, we present experimental data and theoretical analysis to demonstrate that the reduced thermal capacitance has a much larger adverse effect in comparison to the beneficial reduction of the thermal resistance. An implication of the presented results is that, contrary to the adopted wafer thinning practices, SiC Schottky diodes fabricated without wafer thinning have superior surge-current capability.

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Performance of a 650V SiC Diode with Reduced Chip Thickness

Cited by 25 publications

References 2 publications

Practical applications of SiC-MOSFETs and further developments

Practical applications of SiC-MOSFETs and further developments

Understanding the Mechanisms of SiC–Water Reaction during Nanoscale Scratching without Chemical Reagents

The effect of wafer thinning and thermal capacitance on chip temperature of SiC Schottky diodes during surge currents

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