Performance of High-k Dielectric Material for Short Channel Length MOSFET Simulated using Silvaco TCAD Tools

Anizam, Fatin Antasha; Ismail, Lyly Nyl; Sihab, Norsabrina; Sauki, Nur Sa’adah Mohd

doi:10.24191/jeesr.v19i1.019

Cited by 5 publications

(4 citation statements)

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“…A bilayer graphene material with a thickness of 1 nm and a length of 24 nm was then deposited on top of the silicon layer, and the process was repeated. HfO2 with a permittivity of 25 was used in this study [28]. A 2 nm thick layer of HfO2 was placed on top of bilayer graphene with a length of 24 nm, which was followed by the deposition of a WSix with a 3 nm thick layer.…”

Section: Methodsmentioning

confidence: 99%

Optimization of 14 nm double gate Bi-GFET for lower leakage current

Nizam

Hamid²,

Salehuddin³

et al. 2023

TELKOMNIKA

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In recent years, breakthroughs in electronics technology have upgraded the physical properties of the metal oxide semiconductor field effect transistor (MOSFET) toward smaller sizes and improvements in both quality and performance. Hence, the growth field effect transistor (GFET) is being promoted as one of the worthy candidates due to its superior material characteristics. A 14 nm horizontal double-gate bilayer graphene field effect transistor (FET) utilizing high-k and a metal gate, which are composed of hafnium dioxide (HfO2) and tungsten silicide (WSix) respectively. Silvaco ATHENA and ATLAS technology computer-aided design (TCAD) tools are used to simulate the design and electrical properties, while Taguchi L9 orthogonal arrays (OA) are used to optimize the electrical properties. The threshold voltage (VTH) adjustment implant dose, VTH adjustment implant energy, source/drain (S/D) implant dose, and S/D implant energy have all been investigated as process parameters, while the VTH adjustment tilt angle and the S/D implant tilt angle have been investigated as noise factors. When compared to the initial findings before optimization, the IOFF has a value of 29.579 nA/µm, indicating a significant improvement. Findings from the optimization technique demonstrate excellent device performance with an IOFF of 28.564 nA/µm, which is closer to the international technology roadmap for semiconductors (ITRS) 2013 target.

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Section: Methodsmentioning

confidence: 99%

Optimization of 14 nm double gate Bi-GFET for lower leakage current

Nizam

Hamid²,

Salehuddin³

et al. 2023

TELKOMNIKA

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“…The performance of the high K-dielectric medium for MOSFET based on TCAD was evaluated by Anizam et al 11 The goal of the currently available research is to examine the performance of MOSFETs employing various high-k dielectric materials and germanium (Ge) as the gate material. Considering the characteristics of the current-voltage (I-V), the MOSFET's overall performance was examined.…”

Section: Literature Surveymentioning

confidence: 99%

“…In both ID-VD graphs for MOSFET with SiO2 and HfO2, It is obvious that the channel modulation impact is worse on both devices with shorter channels. 11 Nevertheless, there are a number of disadvantages to present strain engineering techniques, including the creation of atomic defects at the interface between silicon and strain inducers and the need for expensive epitaxial depositions which are challenging to implement for flexible electronics made by plastic substrates. 12 High quality graphene is a great conductor that does not have a band gap, which results that it cannot be turned off.…”

Section: Literature Surveymentioning

confidence: 99%

Design and Simulation of Bi-Layer Optimized High K- Dielectric Medium for N-Mosfet with Wild Horse Optimization to Improve Electrical Characteristics

Pavithra Guru

2024

ECS J. Solid State Sci. Technol.

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Electronic devices for advanced modern semiconductor based technology, mainly focus on the design regarding lighter, faster and more affordable solutions to meet the specifications of modern digital electronics. Some of the drawbacks for minimizing device size in MOSFET include gate insulator scaling, Short-Channel Effects (SCEs), shallow junction technology and off-state leakage current in MOSFET devices. In addition, the traditional SiO2 as a dielectric material contains restricted maximum capacitance as well as increased tunnel current leakage due to the thickness. Hence, a High-k dielectric is required to replace SiO2 to overcome the mentioned issues. In this model, the N-type MOSFET is designed based on the bi-layer high K-dielectric medium with optimized thickness according to the maximum capacitance and minimum threshold voltage, which are implemented on VLSI based applications such as 6 T SRAM for evaluating the performance. The drain current of HfO2, Al2O3 and HfO2+Si3N4 for 2.5 v drain voltage are 1.87 mA, 1.51 mA and 3.54 mA. Then, the read and write delay of the single and bi-layer MOSFET are 70.84 ps, 82.64 ps, 95.21 ps and 10.24 ps, 15.47 ps, 21.74 ps. Thus, the designed and simulated bi-layer optimized high k- dielectric medium for N-MOSFET with wild horse optimization performs better electrical characteristics than the single layer dielectric medium MOSFET.

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“…The authors established that HfO2, among the dielectric materials examined, exhibited excellent characteristics since its SCEs were lower than those of the other materials. In [17] , SiO2 was replaced by a high-k dielectric material, HfO2. The researchers demonstrated that HfO2 had fewer SCEs than typical SiO2, including a lower threshold voltage and off-state leakage current, implying that HfO2 might be used as a novel dielectric material to mitigate SCEs.…”

Section: Introductionmentioning

confidence: 99%

Optimizing dielectric constants for enhanced performance in nanoscale DG-FinFETs: A comprehensive study on short channel effects

Nura Muhammad Shehu,

Garba Babaji,

Mutari Hajara Ali

2024

IJBAS

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This study explores how variations in fin and gate dielectric constants impact nanoscale, DG-FinFETs’ sensitivity to Short Channel Effects (SCEs). Various fin (channel) materials; Gallium Arsenide (GaAs), Gallium Antimonide (GaSb), Gallium Nitride (GaN), and Silicon (Si), are considered. PADRE simulation environment is used to investigate the threshold Voltage (Vth) Roll-off, a crucial performance parameter. GaAs-FinFET, with a gate dielectric and fin dielectric constant values of 15 and 45 shows the lowest threshold voltage of 0.412 V. The study concludes that FinFETs with a higher fin dielectric constant than gate dielectric constant exhibit reduced SCEs, leading to lower power consumption, faster switching, and improved efficiency. This underscores the importance of optimizing dielectric constants, especially the fin dielectric constant, for enhanced DG-FinFET performance.

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Performance of High-k Dielectric Material for Short Channel Length MOSFET Simulated using Silvaco TCAD Tools

Cited by 5 publications

References 0 publications

Optimization of 14 nm double gate Bi-GFET for lower leakage current

Optimization of 14 nm double gate Bi-GFET for lower leakage current

Design and Simulation of Bi-Layer Optimized High K- Dielectric Medium for N-Mosfet with Wild Horse Optimization to Improve Electrical Characteristics

Optimizing dielectric constants for enhanced performance in nanoscale DG-FinFETs: A comprehensive study on short channel effects

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