An upgrade program is underway which will bring the luminosity of the LHC up to about 7.5x10 34 cm −2 s −1 in 2027, with the goal of an integrated luminosity of 3000 fb −1 by the end of 2037. This High Luminosity scenario, HL-LHC, will present new challenges of higher data rates and increased radiation hardness for the pixel detector (a non-ionizing fluence of 2x10 16 n eq /cm 2 and an ionizing dose of 10 MGy, is expected on the inner pixel layer for 3000 fb −1 integrated luminosity). To maintain or even improve the performance of the present system, new technologies have to be fully exploited for the so-called Phase-II upgrade. Among them is the future version of front-end chips in 65-nm CMOS by the CERN RD53 Collaboration which supports small pixel sizes of 50x50 or 25x100 µm 2 and lower thresholds (∼ 1000 e − ). For the development of the appropriate planar pixel sensor, CMS has recently launched a submission of n + -p sensors on 6 inch wafers with an active thickness of 150 µm at Hamamatsu. The submission consists of physically thinned, directly bonded and deep diffused wafers with p-stop or p-spray isolation. A variety of sensors with and without biasing scheme is designed to match the different read-out chips (RD53A, ROC4Sens, etc.) and first hybrid modules are assembled at Fraunhofer IZM. In this document, we will present an overview of the Phase II pixel R&D program and report on preliminary results on the HPK submission.
AbstractAn upgrade program is underway which will bring the luminosity of the LHC up to about 7.5x10 34 cm −2 s −1 in 2027, with the goal of an integrated luminosity of 3000 fb −1 by the end of 2037. This High Luminosity scenario, HL-LHC, will present new challenges of higher data rates and increased radiation hardness for the pixel detector (a non-ionizing fluence of 2x10 16 n eq /cm 2 and an ionizing dose of 10 MGy, is expected on the inner pixel layer for 3000 fb −1 integrated luminosity). To maintain or even improve the performance of the present system, new technologies have to be fully exploited for the so-called Phase-II upgrade. Among them is the future version of front-end chips in 65-nm CMOS by the CERN RD53 Collaboration which supports small pixel sizes of 50x50 or 25x100 µm 2 and lower thresholds (∼ 1000 e − ). For the development of the appropriate planar pixel sensor, CMS has recently launched a submission of n + -p sensors on 6 inch wafers with an active thickness of 150 µm at Hamamatsu. The submission consists of physically thinned, directly bonded and deep diffused wafers with p-stop or p-spray isolation. A variety of sensors with and without biasing scheme is designed to match the different read-out chips (RD53A, ROC4Sens, etc.) and first hybrid modules are assembled at Fraunhofer IZM. In this document, we will present an overview of the Phase II pixel R&D program and report on preliminary results on the HPK submission.