Performance optimization of tri-gate junctionless FinFET using channel stack engineering for digital and analog/RF design

Abstract

This manuscript explores the behavior of a junctionless tri-gate FinFET at the nano-scale region using SiGe material for the channel. For the analysis, three different channel structures are used: (a) tri-layer stack channel (TLSC) (Si–SiGe–Si), (b) double layer stack channel (DLSC) (SiGe–Si), (c) single layer channel (SLC) (Si). The I−V characteristics, subthreshold swing (SS), drain-induced barrier lowering (DIBL), threshold voltage (V t), drain current (I ON), OFF current (I OFF), and ON-OFF current ratio (I ON/I OFF) are observed for the structures at a 20 nm gate length. It is seen that TLSC provides 21.3% and 14.3% more ON current than DLSC and SLC, respectively. The paper also explores the analog and RF factors such as input transconductance (g m), output transconductance (g ds), gain (g m/g ds), transconductance generation factor (TGF), cut-off frequency (f T), maximum oscillation frequency (f max), gain frequency product (GFP) and linearity performance parameters such as second and third-order harmonics (g m2, g m3), voltage intercept points (VIP2, VIP3) and 1-dB compression points for the three structures. The results show that the TLSC has a high analog performance due to more g m and provides 16.3%, 48.4% more gain than SLC and DLSC, respectively and it also provides better linearity. All the results are obtained using the VisualTCAD tool.

Performance investigation of stacked-channel junctionless Tri-Gate FinFET 8T-SRAM cell

“…The process variations affect the threshold voltage (V th ) of a device. The V th variation induced by LER is calculated as given in equation (10) [40]- ( )…”

“…Since variability in manufacturing process can aggravate short-channel effects (SCEs), JL FinFET are less susceptible to manufacturing variability due to uniform doping profile [5][6][7][8]. In addition, compound semiconductor materials, such as SiGe, have emerged as promising candidates for channel materials to replace conventional Si for next-generation logic applications because of their superior carrier transport properties [9,10].…”

Simulation based analysis of HK-Ge-Step-FinFET and its usage as inverter & SRAM

“…6.5 × 10 −4 1.9 × 10 −14 3.36 × 10 10 56 3.9 0.5 JL-FinFET [8] 3.6 × 10 −4 7.9 × 10 −13 4.5 × 10 8 74.5 3.9 0.5 Conventional FinFET [14] 3.45 × 10 For the purpose of storing data, cross-coupled inverters are used, whereas access transistors are utilized for the purpose of reading and writing data [43]. Table 5 describes that the SRAM Cell offers three different modes of operation based on control signal values.…”

“…The primary factors that restrict the downsizing of a bulk MOSFET are the power consumption caused by Short Channel outcomes, leakage current, and the degradation of subthreshold swing. Thus, the performance of CMOS designs has also been negatively impacted by technology scaling due to short channel effects [8][9][10][11]. The variety of nonclassical devices, including Double gate (DG), Dual Material Gate (DMG), and Surrounding gate (SG) MOSFETs are suggested in literatures [12].…”