Performance-optimized gate-first 22-nm SOI technology with embedded DRAM

Abstract

IBM's high-performance 22-nm silicon-on-insulator (SOI) technology is the enabling physical foundation of IBM POWER8i processors. This paper describes, for the first time in detail, some of the unique aspects of the silicon processing, the features that enabled the industry-leading chip-level performance, and some aspects of the collaborative approach between technology and design teams that enabled both first-time-right silicon and rapid yield improvement. Most critical to the processor functional capability and power-performance achievements are the high-density on-chip memory in the form of embedded DRAM and the high-performance FET device designs based on a low-parasitic-capacitance gate-first FET architecture. Extensive on-chip analog functions are enabled by an additional comprehensive set of devices available in the technology. Fifteen levels of metal with five metal levels at an 80-nm pitch provide the interconnect and power distribution. We describe the pattern resolution enhancement strategy as well as motivation and structural aspects of the innovative features, from the low-resistance N+ epitaxy substrate under the SOI to a dual-embedded source-drain architecture and a highly scaled gate dielectric.

Compute in‐Memory with Non‐Volatile Elements for Neural Networks: A Review from a Co‐Design Perspective

“…More recently, embedded DRAM (eDRAM) has been used in higher‐level on‐chip cache memory. [ 22 ] Reaching an SRAM cache‐level speed with eDRAM, however, comes at a cost—a larger DRAM cell size (as large as 50F 2 )—however, eDRAM still provides a density advantage. Both SRAM and DRAM are volatile, meaning the stored bits will be lost once the power is off.…”