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A thoroughly updated third edition of an classic and widely adopted text, perfect for practical transistor design and in the classroom. Covering a variety of recent developments, the internationally renowned authors discuss in detail the basic properties and designs of modern VLSI devices, as well as factors affecting performance. Containing around 25% new material, coverage has been expanded to include high-k gate dielectrics, metal gate technology, strained silicon mobility, non-GCA (Gradual Channel Approximation) modelling of MOSFETs, short-channel FinFETS, and symmetric lateral bipolar transistors on SOI. Chapters have been reorganized to integrate the appendices into the main text to enable a smoother learning experience, and numerous additional end-of-chapter homework exercises (+30%) are included to engage students with real-world problems and test their understanding. A perfect text for senior undergraduate and graduate students taking advanced semiconductor devices courses, and for practicing silicon device professionals in the semiconductor industry.

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Silicon nanowire field effect transistor sensors with SiO(2)/HfO(2) as the gate dielectric sensing surface are fabricated using a top down approach. These sensors are optimized for pH sensing with two key characteristics. First, the pH sensitivity is shown to be independent of buffer concentration. Second, the observed pH sensitivity is enhanced and is equal to the Nernst maximum sensitivity limit of 59 mV/pH with a corresponding subthreshold drain current change of ∼ 650%/pH. These two enhanced pH sensing characteristics are attributed to the use of HfO(2) as the sensing surface and an optimized fabrication process compatible with silicon processing technology.

An experimental method is described for directly measuring the probability of electron emission from the silicon substrate into the SiO2 layer after the electron has fallen through a certain potential drop in traversing the depletion layer and reached the Si-SiO2 interface. The method is based on optically induced hot-electron injection in polysilicon-SiO2-silicon field-effect-transistor structures of reentrant geometry. The emission probability was studied as a function of substrate doping profile, substrate voltage, gate voltage, and lattice temperature. It was found that the hot electrons could be emitted by tunneling as well as by surmounting the Schottky-lowered barrier. Over-the-barrier emission dominates at large substrate voltages, where the emission probability is high, and tunnel emission becomes appreciable and may even dominate at small substrate voltages where the emission probability is low. A simple model was developed based on the assumption that only those hot electrons lucky enough to escape collision with optical phonons were emitted. Using this model, we found that the expression P=A exp(−d/λ) described very well the dependence of the emission probability on doping profile, substrate voltage, and gate voltage. Here A=2.9 is a constant, λ is the optical-phonon-electron collision mean free path, d is the distance from the Si-SiO2 interface where the potential energy is equal to the ’’corrected’’ barrier of (3.1 eV−βEOX1/2 −αEOX2/3ox), βEOX1/2 is the Schottky lowering of the barrier, and αEOX2/3 is a ’’barrier-lowering’’ term introduced to account for the probability of tunneling. The temperature dependence of the collision mean free path was found to follow the theoretical relationship λ=λo tanh(ER/2kbT), with λo=108 Å and ER=0.63 eV. This model is useful for evaluating potential hot-electron-related instability problems in IGFET and similar structures.