The ability to deposit and tailor reliable semiconducting films (with a particular recent emphasis on ultrathin systems) is indispensable for contemporary solid-state electronics. The search for thin-film semiconductors that provide simultaneously high carrier mobility and convenient solution-based deposition is also an important research direction, with the resulting expectations of new technologies (such as flexible or wearable computers, large-area high-resolution displays and electronic paper) and lower-cost device fabrication. Here we demonstrate a technique for spin coating ultrathin (approximately 50 A), crystalline and continuous metal chalcogenide films, based on the low-temperature decomposition of highly soluble hydrazinium precursors. We fabricate thin-film field-effect transistors (TFTs) based on semiconducting SnS(2-x)Se(x) films, which exhibit n-type transport, large current densities (>10(5) A cm(-2)) and mobilities greater than 10 cm2 V(-1) s(-1)--an order of magnitude higher than previously reported values for spin-coated semiconductors. The spin-coating technique is expected to be applicable to a range of metal chalcogenides, particularly those based on main group metals, as well as for the fabrication of a variety of thin-film-based devices (for example, solar cells, thermoelectrics and memory devices).

The Lewis acid-catalyzed Diels-Alder reaction of the organic semiconductor pentacene with N-sulfinylacetamide yields a soluble adduct. Spin-coated thin films of this adduct undergo solid-phase conversion to form thin films of pentacene at moderate temperatures. Organic thin film transistors fabricated by spin-coating this adduct, followed by thermal conversion to pentacene, exhibit the highest mobility reported to date for a solution-processed organic semiconductor.

The slow-down in traditional silicon complementary metal-oxide-semiconductor (CMOS) scaling (Moore's law) has created an opportunity for a disruptive innovation to bring the semiconductor industry into a postsilicon era. Due to their ultrathin body and ballistic transport, carbon nanotubes (CNTs) have the intrinsic transport and scaling properties to usher in this new era. The remaining challenges are largely materials-related and include obtaining purity levels suitable for logic technology, placement of CNTs at very tight (∼5 nm) pitch to allow for density scaling and source/drain contact scaling. This review examines the potential performance advantages of a CNT-based computing technology, outlines the remaining challenges, and describes the recent progress on these fronts. Although overcoming these issues will be challenging and will require a large, sustained effort from both industry and academia, the recent progress in the field is a cause for optimism that these materials can have an impact on future technologies.

Carbon nanotubes have potential in the development of high-speed and power-efficient logic applications. However, for such technologies to be viable, a high density of semiconducting nanotubes must be placed at precise locations on a substrate. Here, we show that ion-exchange chemistry can be used to fabricate arrays of individually positioned carbon nanotubes with a density as high as 1 × 10(9) cm(-2)-two orders of magnitude higher than previous reports. With this approach, we assembled a high density of carbon-nanotube transistors in a conventional semiconductor fabrication line and then electrically tested more than 10,000 devices in a single chip. The ability to characterize such large distributions of nanotube devices is crucial for analysing transistor performance, yield and semiconducting nanotube purity.

The isolation of semiconducting carbon nanotubes (CNTs) to ultrahigh (ppb) purity is a prerequisite for their integration into high-performance electronic devices. Here, a method employing column chromatography is used to isolate semiconducting nanotubes to 99.9% purity. The study finds that by modifying the solution preparation step, both the metallic and semiconducting fraction are resolved and elute using a single surfactant system, allowing for multiple iterations. Iterative processing enables a far more rapid path to achieving the level of purities needed for high performance computing. After a single iteration, the metallic peak in the absorption spectra is completely attenuated. Although absorption spectroscopy is typically used to characterize CNT purity, it is found to be insufficient in quantifying solutions of high purity (>98 to 99%) due to low signal-to-noise in the metallic region of ultrahigh purity solutions. Therefore, a high throughput electrical testing method was developed to quantify the degree of separation by characterizing ∼4000 field-effect transistors fabricated from the separated nanotubes after multiple iterations of the process. The separation and characterization methods described here provide a path to produce the ultrahigh purity semiconducting CNT solutions needed for high performance electronics.