Performance tuning of iterative algorithms in signal processing

Pohl, Z.; Kadlec, J.; Šůcha, Přemysl; Hanzdlek, Z.

doi:10.1109/fpl.2005.1515816

Cited by 6 publications

(7 citation statements)

References 9 publications

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“…Cyclic scheduling presented in [16] is not dependent on the period length and with respect to [15] it leads to simpler problem formulation with less integer variables. Moreover, this model allows to reduce number of interconnections by minimization of the data transfers as shown in [17]. Modulo scheduling and software pipelining [18,19], usually used in the compiler community, are alternative terms to cyclic scheduling, used in the scheduling community.…”

Section: Related Work On Scheduling Of Iterative Algorithmsmentioning

confidence: 99%

Scheduling of Iterative Algorithms with Matrix Operations for Efficient FPGA Design—Implementation of Finite Interval Constant Modulus Algorithm

Šůcha

Hanzálek

Hermanek

et al. 2007

J VLSI Sign Process Syst Sign Image Video Technol

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This paper deals with the optimization of iterative algorithms with matrix operations or nested loops for hardware implementation in Field Programmable Gate Arrays (FPGA), using Integer Linear Programming (ILP). The method is demonstrated on an implementation of the Finite Interval Constant Modulus Algorithm. It is an equalization algorithm, suitable for modern communication systems (4G and behind). For the floatingpoint calculations required in the algorithm, two arithmetic libraries were used in the FPGA implementation: one based on the logarithmic number system, the other using floating-point number system in the standard IEEE format. Both libraries use pipelined modules. Traditional approaches to the scheduling of nested loops lead to a relatively large code, which is unsuitable for FPGA implementation. This paper presents a new high-level synthesis methodology, which models both, iterative loops and imperfectly nested loops, by means of the system of linear inequalities. Moreover, memory access is considered as an additional resource constraint. Since the solutions of ILP formulated problems are known to be computationally intensive, an important part of the article is devoted to the reduction of the problem size.

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Section: Related Work On Scheduling Of Iterative Algorithmsmentioning

confidence: 99%

Scheduling of Iterative Algorithms with Matrix Operations for Efficient FPGA Design—Implementation of Finite Interval Constant Modulus Algorithm

Šůcha

Hanzálek

Hermanek

et al. 2007

J VLSI Sign Process Syst Sign Image Video Technol

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“…That is why an iterative scheduling of the lattice order update loop was performed [10]. It was found ADD macro pipe utilised less than 25%.…”

Section: Lattice Filter Hw Designmentioning

confidence: 99%

“…The possibilities of efficient implementation of the RLS lattice algorithm was exhaustively investigated in [9,10]. The resulting IP cores outperform floating-point DSP microprocessor solutions by one order of magnitude.…”

Section: Introductionmentioning

confidence: 99%

RLS Lattice Algorithm with Order Probability Evaluation as an Accelerator for the Microblaze Processor

Pohl

Tichý

2007

2007 International Conference on Field Programmable Logic and Applications

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A high performance RLS lattice filter with evaluation of an unknown order of identified system was implemented as an accelerator PCORE for Xilinx EDK. The accelerator hardware can fully exploit parallelisms in the algorithm and remove load from a microprocessor. The EDK integration allows effective programing and debugging of a hardware accelerated DSP applications. The optimal logarithmic number system implementation of the RLS lattice IP core was used. Additionally, the extension by the order probability evaluation was implemented. Then, the core was wrapped in the System Generator. Finally, the generated EDK PCORE was modified to independent clock operation. Implemented solution makes possible evaluation of the RLS lattice filter of order 256 at 8 kHz input data rate in the best case. At the same time the order probability can be maintained. The implementation outperforms software solution up to 74 times and it is also performing 40% faster than other known solutions.

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“…Cyclic scheduling presented inŠůcha et al [2004] is not dependent on the period length and with respect to Fimmel and Müller [2001] it leads to simpler problem formulation with less integer variables. Moreover, this model allows to reduce number of interconnections by minimization of the data transfers as shown in Pohl et al [2005]. Modulo scheduling and software pipelining [Rau and Glaeser, 1981] are related terms to cyclic scheduling, which are usually used in the compiler community.…”

Section: Related Workmentioning

confidence: 99%