Performance Variation According to Device Structure and the Source/Drain Metal Electrode of a-IGZO TFTs

Rha, Sang Ho; Jung, Jongwan; Jung, Yoonsoo; Chung, Yoon Jang; Kim, Un Ki; Hwang, Eun Suk; Park, Byoung Keon; Park, Tae Joo; Choi, Jung-Hae; Hwang, Cheol Seong

doi:10.1109/ted.2012.2220367

Cited by 37 publications

(17 citation statements)

References 19 publications

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“…16 If a-IGZO top surface is damaged during the wet etching, the sub-threshold swing (SS) of top gate sweep would be larger compared to that of bottom gate sweep. 17 However, the SS of the top gate sweep is quite small (0.29V/dec.) and similar to bottom gate sweep (0.21V/dec.).…”

Section: Resultsmentioning

confidence: 99%

Effect of top gate potential on bias-stress for dual gate amorphous indium-gallium-zinc-oxide thin film transistor

Chun

Park

et al. 2016

AIP Advances

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We report the abnormal behavior of the threshold voltage (VTH) shift under positive bias Temperature stress (PBTS) and negative bias temperature stress (NBTS) at top/bottom gate in dual gate amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs). It is found that the PBTS at top gate shows negative transfer shift and NBTS shows positive transfer shift for both top and bottom gate sweep. The shift of bottom/top gate sweep is dominated by top gate bias (VTG), while bottom gate bias (VBG) is less effect than VTG. The X-ray photoelectron spectroscopy (XPS) depth profile provides the evidence of In metal diffusion to the top SiO2/a-IGZO and also the existence of large amount of In+ under positive top gate bias around top interfaces, thus negative transfer shift is observed. On the other hand, the formation of OH− at top interfaces under the stress of negative top gate bias shows negative transfer shift. The domination of VTG both on bottom/top gate sweep after PBTS/NBTS is obviously occurred due to thin active layer.

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Section: Resultsmentioning

confidence: 99%

Effect of top gate potential on bias-stress for dual gate amorphous indium-gallium-zinc-oxide thin film transistor

Chun

Park

et al. 2016

AIP Advances

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“…It is an artifact error for the negative value of R SD (L = 0 μm) at the annealing temperature of 250 °C, regardless of L variation with respect to the V GS . For the ohmic contact of the device annealed at 300 °C, the L variation is negligible, so that this problem was not happened 25 .…”

Section: Resultsmentioning

confidence: 99%

Induced nano-scale self-formed metal-oxide interlayer in amorphous silicon tin oxide thin film transistors

Liu

Ning

et al. 2018

Sci Rep

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Amorphous Silicon-Tin-Oxide thin film transistors (a-STO TFTs) with Mo source/drain electrodes were fabricated. The introduction of a ~8 nm MoOx interlayer between Mo electrodes and a-STO improved the electron injection in a-STO TFT. Mo adjacent to the a-STO semiconductor mainly gets oxygen atoms from the oxygen-rich surface of a-STO film to form MoOx interlayer. The self-formed MoOx interlayer acting as an efficient interface modification layer could conduce to the stepwise internal transport barrier formation while blocking Mo atoms diffuse into a-STO layer, which would contribute to the formation of ohmic contact between Mo and a-STO film. It can effectively improve device performance, reduce cost and save energy for the realization of large-area display with high resolution in future.

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“…It is an artifact error for the negative value of R SD (L=0 μm) at the annealing temperature of 250℃, regardless of L variation with respect to the V GS . For the ohmic contact of the device annealed at 300℃, the L variation is negligible, so that this problem was not happened 26 . For the best performance of a-STO TFT annealed at 300℃, a focused ion beam transmission electron microscope (FIB-TEM) is utilized to analyze the interface of Mo and a-STO film.…”

Section: Resultsmentioning

confidence: 99%

35.3: Self‐formed nano‐scale metal‐oxide contact interlayer for amorphous silicon tin oxide TFTs

Ning

Liu

et al. 2018

Symp Digest of Tech Papers

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The formation of metal oxide interlayer is induced by pre‐annealing process in the amorphous Silicon‐Tin‐Oxide thin film transistors (a‐STO TFTs) with Mo source/drain electrodes. Cross‐sectional high‐resolution transmission electron microscopy image confirmed the formation of ~8nm MoOx interlayer. The introduction of MoOx interlayer between Mo electrodes and a‐STO improved the electron injection in a‐STO TFT. Mo adjacent to the a‐STO semiconductor gets oxygen atoms from the oxygen‐rich surface of a‐STO film to form MoOx interlayer. The self‐formed MoOx interlayer acting as an efficient interface modification layer could conduce to the stepwise internal transport barrier formation while blocking Mo atoms diffuse into a‐STO layer, which would contribute to the formation of ohmic contact between Mo and a‐STO film.

show abstract

Performance Variation According to Device Structure and the Source/Drain Metal Electrode of a-IGZO TFTs

Cited by 37 publications

References 19 publications

Effect of top gate potential on bias-stress for dual gate amorphous indium-gallium-zinc-oxide thin film transistor

Effect of top gate potential on bias-stress for dual gate amorphous indium-gallium-zinc-oxide thin film transistor

Induced nano-scale self-formed metal-oxide interlayer in amorphous silicon tin oxide thin film transistors

35.3: Self‐formed nano‐scale metal‐oxide contact interlayer for amorphous silicon tin oxide TFTs

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