Performances of a Capacitorless 1T-DRAM Using Polycrystalline Silicon Thin-Film Transistors With Trenched Body

Lin, Jyi-Tsong; Huang, Kuo-Ming; Jheng, Bao-Tang

doi:10.1109/led.2008.2004632

Cited by 19 publications

(3 citation statements)

References 11 publications

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“…(poly-Si) thin-film transistors (TFTs) have been extensively studied for driving circuit of display panel, static random access memory (SRAM), dynamic random access memory, non-volatile memory, and three-dimensional integrated circuit (3D-IC) [1][2][3][4][5][6][7]. For the requirements of system-on-chip, high-performance devices and low-power devices need to be integrated in the same chip [8][9][10].…”

Section: Olycrystalline-siliconmentioning

confidence: 99%

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Impacts of Vertically Stacked Monolithic 3D-IC Process on Characteristics of Underlying Thin-Film Transistor

Cheng-Yu

Huang

Chen

et al. 2020

IEEE J. Electron Devices Soc.

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In this work, the high-performance junctionless-mode (JL) and low-power inversion-mode (IM) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) with nanosheet channels (less than 10-nm in thickness) are vertically integrated in monolithic three-dimensional integrated circuit (3D-IC) structure. Both JL and IM TFTs can exhibit high on/off current ratio over 10 7 to demonstrate their performance. The JL TFT has much higher on-state current ~ 24 times than it of the IM TFT. And the IM-TFT has much lower SS ~ 0.104 V/decade and off-current ~ 0.04 times than them of the JL TFT. However, the fabrication of the top-devices (JL TFTs) would degrade the performance of underlying-devices (IM TFTs), resulting in the threshold voltage shift of the IM TFTs from 0.61 to 2.17 V, SS increase from 0.104 to 0.218 V/decade and on-state current degradation from 16 to 3 A. In order to further understand the reasons, the IM TFT with top-device removal process is also fabricated, which exhibits a partial recovery in performance. The results indicate the presence and fabrication process of the top-device would lead to the defect generation in the underlying-device. The results provide a new consideration for monolithic 3D-IC manufacturing technology. Index Terms-Monolithic 3D-IC; nanosheet channel; low power; thin-film transistor.

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Section: Olycrystalline-siliconmentioning

confidence: 99%

“…The ID-VD curves of IM poly-Si TFT (underlying-device) with different fabrication process. Plots of ln[ID/(VGS -VFB)] versus 1/( VGS -VFB)2 curves of IM poly-Si TFT (underlying-device) with different fabrication process for the NGB extraction. The flat-band voltage VFB is defined as the gate voltage that yields the minimum drain current from the ID-VG curves.…”

mentioning

confidence: 99%

Impacts of Vertically Stacked Monolithic 3D-IC Process on Characteristics of Underlying Thin-Film Transistor

Cheng-Yu

Huang

Chen

et al. 2020

IEEE J. Electron Devices Soc.

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“…In recent years, 1T-DRAM devices with poly-Si bodies have been studied to overcome the limitations of silicon 1T-DRAM [15][16][17][18][19][20][21][22][23][24][25][26]. Since the poly-Si devices use grain boundaries (GBs) instead of a FB as a charge storage region, they can perform memory operations in a FD-SOI structure [15].…”

Section: Introductionmentioning

confidence: 99%

Analysis of a Lateral Grain Boundary for Reducing Performance Variations in Poly-Si 1T-DRAM

2020

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A capacitorless one-transistor dynamic random-access memory device that uses a poly-silicon body (poly-Si 1T-DRAM) has been suggested to overcome the scaling limit of conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). A poly-Si 1T-DRAM cell operates as a memory by utilizing the charge trapped at the grain boundaries (GBs) of its poly-Si body; vertical GBs are formed randomly during fabrication. This paper describes technology computer aided design (TCAD) device simulations performed to investigate the sensing margin and retention time of poly-Si 1T-DRAM as a function of its lateral GB location. The results show that the memory’s operating mechanism changes with the GB’s lateral location because of a corresponding change in the number of trapped electrons or holes. We determined the optimum lateral GB location for the best memory performance by considering both the sensing margin and retention time. We also performed simulations to analyze the effect of a lateral GB on the operation of a poly-Si 1T-DRAM that has a vertical GB. The memory performance of devices without a lateral GB significantly deteriorates when a vertical GB is located near the source or drain junction, while devices with a lateral GB have little change in memory characteristics with different vertical GB locations. This means that poly-Si 1T-DRAM devices with a lateral GB can operate reliably without any memory performance degradation from randomly determined vertical GB locations.

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Improving retention time in tunnel field effect transistor based dynamic memory by back gate engineering

Navlakha

Lin

Kranti

2016

Journal of Applied Physics

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In this work, we report on the impact of position, bias, and workfunction of back gate on retention time of Tunnel Field Effect Transistor (TFET) based dynamic memory in ultra thin buried oxide and Double Gate (DG) transistors. The front gate of the TFET is aligned at a partial portion of the semiconductor film and controls the read mechanism based on band-to-band tunneling. The back gate is engineered to improve the performance of the dynamic cell by positioning it at the region uncovered by the front gate where it forms a deep potential well. The physical well formed by the back gate misalignment is made more profound by using a p+ poly workfunction as it accumulates more holes in the storage region and forms a deep potential well that sustains holes for longer duration, thereby increasing the retention time. The retention time is also governed by the generation and recombination phenomenon which can be controlled through the applied bias at the back gate. The retention time attained is ∼2 s at a temperature of 85 °C through optimal back gate engineering in DG transistors. The work shows innovative viewpoints of transforming gate misalignment, traditionally considered detrimental into a unique opportunity, coupled with appropriate selection of back gate workfunction and bias to significantly improve the retention time of capacitorless dynamic memory.

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Performances of a Capacitorless 1T-DRAM Using Polycrystalline Silicon Thin-Film Transistors With Trenched Body

Cited by 19 publications

References 11 publications

Impacts of Vertically Stacked Monolithic 3D-IC Process on Characteristics of Underlying Thin-Film Transistor

Impacts of Vertically Stacked Monolithic 3D-IC Process on Characteristics of Underlying Thin-Film Transistor

Analysis of a Lateral Grain Boundary for Reducing Performance Variations in Poly-Si 1T-DRAM

Improving retention time in tunnel field effect transistor based dynamic memory by back gate engineering

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