Performances of accumulation-mode n- and p-MOSFETs on Si(110) wafers

Abstract

In this study, we investigate the electrical and noise performances of accumulation-mode n- and p-MOSFETs on Si(110) wafers and compare them with conventional MOSFETs fabricated either on Si(100) or Si(110) wafers. With regard to electrical performances, accumulation-mode p-type MOSFETs are in every aspect superior. However, its n-type counterpart does not provide the best performances even though they are still superior to conventional transistors when fabricated on the same type of wafer. Conventional inversion-mode n-MOSFETs on Si(100) wafers still display the best performances. The simultaneous improvement and reduction in drivability respectively in the p- and n-type transistors make the accumulation-mode MOSFETs fabricated on Si(110) wafers extremely well suited for complementary technologies owing to their great balance in terms of drivability. With regard to noise evaluation, accumulation-mode MOSFETs on Si(110) wafers exhibit the highest noise level even though they compare relatively well with the inversion transistors on Si(110) wafers, especially for p-type ones. The lowest noise level is obtained for conventional inversion-mode MOSFETs on Si(100) wafers, and the type of wafer upon which transistors are fabricated is the reason. Indeed, the fabrication of high-quality Si/SiO2 interfaces is better achieved for silicon wafers with a (100) crystallographic orientation, leading to few interface defects and consequently less noise.

Observation of the Magnetization Reorientation in Self-Assembled Metallic Fe-Silicide Nanowires at Room Temperature by Spin-Polarized Scanning Tunneling Spectromicroscopy

“…Moreover, the complementary metal-oxide-semiconductor field-effect transistor (CMOSFET) on Si(110) could be a promising alternative because the p-type CMOSFET switch is about 30% faster in the (110) substrate compared with the (100) substrate, and CMOSFET on Si(110) exhibits a higher hole mobility than those on Si(100) [19]. Thus, the self-assembly of large-area magnetic silicide NWs on Si(110) surfaces opens up the possibility for future wafer-scale integration of high-density Si-based spintronic nanodevices in a bottom-up scheme.…”

Carrier Mobility in Field-Effect Transistors

“…Even though making use of the majority carriers to generate the current [36,37] is already known and has been investigated more than 40 years ago, this approach has recently gained interest, and recent studies have positioned the accumulation-mode MOSFETs as serious competitors [13,14,[38][39][40][41] to take over the conventional transistors for future CMOS technologies. Scarce data have been published so far regarding the carrier mobility flowing inside an accumulation layer [14,36], and a method to extract it from the conventional mobility measurement is proposed here since in accumulation-mode MOSFETs the conduction, and thus, the measured mobility involves the conduction inside the accumulation layer and the conduction occurring inside the SOI layer.…”

Aplicação de transistores SOI sem junções em espelhos de corrente de diferentes arquiteturas

“…Dessa forma, o SOI pMOSFET, mostrado na Figura 7 e na Figura 8, considera a tensão de corpo G2 fixa, onde Ib representa a corrente de corpo, Iacc a corrente de acumulação, VG1 é a tensão de porta principal, VG2 é o tensão de porta secundária, VS é a tensão de fonte, e VD é a tensão de dreno do dispositivo [3], [41], [47]. Além disso, o comportamento do transistor nMOS da mesma tecnologia pode ser deduzido desse mesmo exemplo, apenas considerando a diferença de mobilidade dos portadores livres [48].…”