Persist Level Parallelism: Streamlining Integrity Tree Updates for Secure Persistent Memory

Freij, Alexander; Yuan, Shougang; Zhou, Huiyang; Solihin, Yan

doi:10.1109/micro50266.2020.00015

Cited by 21 publications

(14 citation statements)

References 55 publications

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“…Therefore, besides the already existing components in modern processors, ProMT requires a small cache to cache the MQ descriptors and a persistent register to persist the hot MT root. On the other hand, Freij et al [20] scheme, assumes a large pipeline and redundant hashing engines to update the MT root. Schemes like Anubis [58] and Phoenix [11] assume a single persistent register.…”

Section: Design Discussionmentioning

confidence: 99%

“…The performance overhead of this operation stems from the sequential hashing process of the whole MT branch. Moreover, the latency of each hashing operation can be 40-80 cycles, which resides on the critical path of the memory writes [20,31,44]. Moreover, the MT branch depth exceeds 10 levels for practical size NVMs, and due to the atomicity requirement, these updates need to be held in the write buffer until the root is updated.…”

Section: Motivationmentioning

confidence: 99%

“…This trust boundary limitation mandates providing security measures, (i.e., memory encryption and integrity verification), to protect the memory content. Counter mode encryption and integrity trees are used in state-of-the-art schemes to meet these security requirements [18,20,42,43,45,47].…”

Section: Introductionmentioning

confidence: 99%

“…Third, before persisting the updates, the integrity tree root needs to be updated by hashing all the updated branch levels. Clearly, updating the integrity tree root resides on the critical path of the write operation, and for a 3TBs memory, the integrity tree can reach 11 levels and a root, which takes 440-880 cycles to complete using a 40-80 cycle hashing function [20,31,44]. Moreover, these 11 updates of the integrity tree, the encryption counter update, the MAC value, and the data cache line need to be held in the write buffer until the root has been successfully updated, thus filling the processor buffers and stalling the execution.…”

Section: Introductionmentioning

confidence: 99%

“…However, the overheads of updating the integrity tree root was rarely studied until recently. Freij et al [20] discussed the overheads of crash consistency requirements in light of the enforced persist ordering, and proposed a Persist Level Parallelism (PLP) optimizations to reduce these overheads. However, the PLP optimizations are discussing the ordering, possible overlapping of the integrity tree updates, and assume a pipeline large enough to perform the updates of the WPQ entries, which can be 32-64 entries.…”

Section: Introductionmentioning

confidence: 99%

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Current computer systems are vulnerable to a wide range of attacks caused by the proliferation of accelerators, and the fact that current system comprise multiple SoCs provided from different vendors. Thus, major processor vendors are moving towards limiting the trust boundary to the processor chip only as in Intel's SGX, and AMD's SME. This secure boundary limitation requires protecting the memory content against data remanence attacks, which were performed against DRAM in the form of cold-boot attack and are more successful against NVM due to NVM's data persistency feature. However, implementing secure memory features, such as memory encryption and integrity verification has a non-trivial performance overhead, and can significantly reduce the emerging NVM's expected lifetime. Previous work looked at reducing the overheads of the secure memory implementation by packing more counters into a cache line, increasing the cacheability of security metadata, slightly reducing the size of the integrity tree, or using the ECC chip to store the MAC values. However, the root update process is barely studied, which requires a sequential update of the MAC values in all the integrity tree levels.In this paper, we propose ProMT, a novel memory controller design that ensures a persistently secure system with minimal overheads. ProMT protects the data confidentiality and ensures the data integrity with minimal overheads. ProMT reduces the performance overhead of secure memory implementation to 11.7%, extends the NVM's life time by 3.59x, and enables the system recovery in a fraction of a second. CCS CONCEPTS• Security and privacy → Hardware-based security protocols.

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Section: Design Discussionmentioning

confidence: 99%

Section: Motivationmentioning

confidence: 99%