Perspective of FinFETs for analog applications

Kilchytska, Valeriya; Collaert, N.; Rooyackers, R.; Lederer, Dimitri; Raskin, J.-P.; Flandre, Denis

doi:10.1109/essder.2004.1356489

Cited by 48 publications

(30 citation statements)

References 2 publications

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“…As the fin width decreases, the gate control over the channel improves and SCE decreases. However, many disadvantages degrade the performance of FinFET [7][8][9]. For instance, by decreasing the fin width, parasitic source/drain (S/D) resistance will enhance, which degrade the drive current and the transconductance in the devices.…”

Section: Introductionmentioning

confidence: 99%

A novel nanoscale fin field effect transistor by amended channel: Investigation and fundamental physics

Karimi

Orouji

2015

Physica E: Low-dimensional Systems and Nanostructures

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Section: Introductionmentioning

confidence: 99%

A novel nanoscale fin field effect transistor by amended channel: Investigation and fundamental physics

Karimi

Orouji

2015

Physica E: Low-dimensional Systems and Nanostructures

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“…The stronger control decreases the subthreshold leakage, threshold voltage roll off, and off state current which makes the scaling possible to meet the ITRS trends [2]. Further, the triple gate FinFET has reduced the doping concentration required in the channel to the extent of 10 15 /cm 3 . However, variation in the height and width of the trigate is now an issue and needs to be tightly controlled.…”

Section: Introductionmentioning

confidence: 99%

“…However, variation in the height and width of the trigate is now an issue and needs to be tightly controlled. In FinFETs, It has been observed that with decreases in fin-width (SCE) short channel effects can be reduced but with reduced fin-width performance of the FinFET may degrade due to increase in parasitic drain/source resistance which leads to reduction of drive current and transconductance of the device [3][4][5]. Also, with smaller fin width, heat cannot flow through easily and device temperature increases.…”

Section: Introductionmentioning

confidence: 99%

Modelling, Design, and Performance Comparison of Triple Gate Cylindrical and Partially Cylindrical FinFETs for Low-Power Applications

Rai

Sahu²,

Dattatray

et al. 2012

ISRN Electronics

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Correspondence should be addressed to Sanjeev Rai, sanjeev rai96@yahoo.com The FinFETs recently have been the rallying point for the engineers as far as the development of the technology is concerned. The authors here have tried successfully to compare the performance of 30 nm conventional triple gate (Conv) FinFET structure with that of partially cylindrical (PC) FinFET. In PC-FinFET the fin is divided into two regions. Region I is partially cylindrical and has curvature of half of the fin width, and Region II is like a conventional FinFET (having flat region). The results show that there is considerable improvement in Ion, Ioff, and subsequent suppression of short channel effects, that is, subthreshold slope, DIBL, self heating effect, and so forth. The improvement has also been felt in series resistance in PC-FinFET as compared to C-FinFET. It is noteworthy also to mention that in PC-FinFET the corner of fin is rounded thus reducing the side wall area which further reduces the gate capacitance reducing the intrinsic delay. The DC and transient analysis of CMOS inverter using C-FinFET and PC-FinFET have been done which shows that PC-FinFET inverter has reduced propagation delay as compared to C-FinFET.

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“…It has been shown that such a device has a very high potential for analog applications due to its high value of early voltage and, hence, a large intrinsic gain [7], [8]. For future System-on-Chip solutions, it is very important to realize basic analog building blocks using FinFETs.…”

Section: Introductionmentioning

confidence: 99%

A Novel and Robust Approach for Common Mode Feedback Using IDDG FinFET

Shrivastava

Baghini

Sachid

et al. 2008

IEEE Trans. Electron Devices

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Abstract-In this paper, we propose a novel and robust approach for common mode feedback (CMFB) for a differential amplifier using independently driven double gate (IDDG) FinFET technology. The performance of a differential amplifier with and without the proposed CMFB scheme is compared using 2-D mixed mode device and circuit simulations. It is shown from extensive simulation results that it is possible to achieve a common mode rejection ratio of 90 dB with improved performance in terms of area, power, and bandwidth even in the presence of process variations. Stability analysis shows that the proposed CMFB scheme does not need any compensating network. The idea is validated using extensive mixed-mode circuit simulations on IDDG FinFET circuits in sub-45-nm node technologies.Index Terms-Common mode feedback (CMFB), FinFET, independently driven double gate (IDDG), mixed signal.

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Perspective of FinFETs for analog applications

Cited by 48 publications

References 2 publications

A novel nanoscale fin field effect transistor by amended channel: Investigation and fundamental physics

A novel nanoscale fin field effect transistor by amended channel: Investigation and fundamental physics

Modelling, Design, and Performance Comparison of Triple Gate Cylindrical and Partially Cylindrical FinFETs for Low-Power Applications

A Novel and Robust Approach for Common Mode Feedback Using IDDG FinFET

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