PET system synchronization and timing resolution using high-speed data links

Abstract

Abstract-Current PET systems with fully digital trigger rely on early digitization of detector signals and the use of digital processors, usually FPGAs, for recognition of valid gamma events on single detectors. Timestamps are assigned and later used for coincidence analysis. In order to maintain a decent timing resolution for events detected on different acquisition boards, it is necessary that local timestamps on different FPGAs be synchronized. Sub-nanosecond accuracy is mandatory if we want this effect to be negligible on overall timing resolution. This is usually achieved by connecting all boards to a common backplane with a precise clock delivery network; however, this approach forces a rigid structure on the whole PET system and may pose scalability problems.As an alternative, we propose a backplane-less PET system architecture in which DAQ boards are connected by single fullduplex high-speed data links. Data encoding with embedded clock is used to correct frequency differences between local oscillators. Timestamp synchronization between FPGAs with clock period resolution is maintained by means of data transfers in a way similar to the IEEE 1588 standard. Finer resolution is achieved by reflection of received clocks and phase difference measurement on the transmitter. It is crucial that data transceivers have very low latency uncertainty in order to achieve the desired timestamp accuracy; we discuss the availability of off-the-shelf hardware for these implementations.

Fixed-Latency, Multi-Gigabit Serial Links With Xilinx FPGAs

“…Some projects about the topic of clock synchronization are described in [7]- [9] and an interesting approach to the problem is proposed by the White Rabbit project [10]. Some fixed latency links with FPGA-embedded transceivers have been implemented [11], [12], but up to now implementations required to fan in the same reference clock both to the transmitter and to the receiver.…”