Phase difference analysis technique for parametric faults BIST in CMOS analog circuits

Wannaboon, Chatchai; Jiteurtragool, Nattagit; San-Um, Wimol; Tachibana, Masayoshi

doi:10.1587/elex.15.20180175

Cited by 10 publications

(2 citation statements)

References 14 publications

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“…In this section we present extensive transistor-level simulation results validating the proposed op amp defect detection and localization technique using two circuits: a twostage folded cascode amplifier and a two-stage telescopic op amp. Multiple op amp defect detection techniques [20,29,37,38] presented in literature are tested against the simple five-transistor differential amplifier followed by a common source (CS) stage and as such do not include cascode transistors which are common in several high-performance op amp topologies [39][40]. As a result, we chose these op amp topologies to validate our method.…”

Section: Defect Simulations and Resultsmentioning

confidence: 99%

Defect Detection and Localization in Operational Amplifiers using Digital Control and Monitor Circuits

Sekyere,

Marampally,

Chen

2023

Preprint

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Operational amplifiers (op amps) are fundamental blocks that find wide application both as stand-alone devices and as crucial building blocks embedded in various Systems on Chips (SoCs). Achieving high defect coverage as well as performing diagnosis and defect localization in these circuits has been proven to be a difficult/expensive task even with sophisticated analog and digital testing circuitry. ISO26262 Standard for functional safety (FuSa) places stringent requirement that an automotive IC must have a very high defect coverage (usually greater than 90%). This reinforce the need to improve the robustness in the design of analog and mixed signal (AMS) circuits to ensure their reliability especially if they are used in mission critical industries. This paper presents a simple defect detection, diagnosis, and localization method for op amps including Widlar current reference and biasing circuitry and can be used both for production and in-field tests for online health monitoring to ensure continued reliability during integrated circuits’ (IC) lifetime. We rigorously validate all our results using extensive transistor-level simulations of two op amps architectures (folded cascode and telescopic) designed in MUSE TSMC 180nm technology. For the folded cascode op amp, the proposed method achieves a worst-case defect coverage of 94.5% and a best-case coverage of 98%. Similarly for the telescopic op amp, the proposed method attains a worst- and best-case defect coverage of 97% and 99% respectively. Furthermore, in this work, we also propose a defect diagnosis and localization strategy using recorded bit streams from states of digital injectors and detectors.

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Section: Defect Simulations and Resultsmentioning

confidence: 99%

Defect Detection and Localization in Operational Amplifiers using Digital Control and Monitor Circuits

Sekyere,

Marampally,

Chen

2023

Preprint

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“…Another approach of the OBIST system is to compare a fault-free circuit to a faulty circuit, and the difference of the counted pulses can be estimated, highlighting the level of parametric faults in the CUT [9]. Similarly to the OBIST system presented in Reference [9], a phase shift between fault-free and faulty circuits could be estimated [35]. In the case of catastrophic fault detection, an on-chip Schmitt oscillator could be used as a reference signal for counting CUT pulses, but such approach cannot be used for the detection of parametric faults [28].…”

Section: Discussionmentioning

confidence: 99%

Design of an Oscillation-Based BIST System for Active Analog Integrated Filters in 0.18 µm CMOS

2019

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In this paper, an oscillation-based built-in self-test system for active an analog integrated circuit is presented. This built-in self-test system was used to detect catastrophic and parametric faults, introduced during chip manufacturing. As circuits under test (CUT), second-order Sallen-Key, Akerberg-Mossberg and Tow-Thomas biquad filters were designed. The proposed test hardware detects parametric and catastrophic faults on changeable limits. The influence of both oscillation and test hardware on fault detection limits were investigated and analyzed. The proposed oscillation based self-test system was designed and simulated in 0.18 µm complementary metal-oxide semiconductor (CMOS) technology. Due to the easiness of implementation and configuration for testing of different active analog filters, such self-test systems can be effectively used in modern integrated circuits, made of a large number of devices and circuits, such as the multi-standard transceivers used in the core hardware of software-defined radios. Using the proposed test strategy, the fault tolerance limits for catastrophic faults varied from 96% to 100% for all injected faults in different structures of low pass filters (LPF). The detection range of parametric faults of passive components’ nominal value, depending on the used structure of the filter, did not exceed –0.74% – 0.72% in case of Sallen-Key, –3.31% – 1.00% in case of Akerberg-Mossberg and –2.39% – 1.44% in case of Tow-Thomas LPF.

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Experimental Verification of a New Oscillation-based Test Algorithm for Analog Circuits

Parai

Srimani

Ghosh

et al. 2021

IETE Journal of Research

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Phase difference analysis technique for parametric faults BIST in CMOS analog circuits

Cited by 10 publications

References 14 publications

Defect Detection and Localization in Operational Amplifiers using Digital Control and Monitor Circuits

Defect Detection and Localization in Operational Amplifiers using Digital Control and Monitor Circuits

Design of an Oscillation-Based BIST System for Active Analog Integrated Filters in 0.18 µm CMOS

Experimental Verification of a New Oscillation-based Test Algorithm for Analog Circuits

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