Phase Frequency Detector and Charge Pump for Low Jitter PLL Applications

Abstract

In this paper a new technique is presented to improve the jitter performance of conventional phase frequency detectors by completely removing the unnecessary one-shot pulse. This technique uses a variable pulse-height circuit to control the unnecessary one-shot pulse height. In addition, a novel charge-pump circuit with perfect current-matching characteristics is used to improve the output jitter performance of conventional charge pumps. This circuit is composed of a pair of symmetrical pump circuits to obtain a good current matching. As a result, the proposed charge-pump circuit has perfect current-matching characteristics, wide output range, no glitch output current, and no jump output voltage. In order to verify such operation, circuit simulation is performed using 0.18 μm CMOS process parameters.

A simulation based performance evaluation of optical ethernet switch

“…This is due to the fact that the inter-packet gap for both high priority (HP traffic) and low priority (LP traffic) is not preserved which leads to the observation of this measured value. And also, the nonpreemptive scheduling algorithm in ethernet switch introduces synchronization problem and jitter [17][18][19][20][21][22][23]. Due to synchronization problem, PDV is going down or decreasing in the range [0.3, 0.4] and [0.5, 0.6] As discussed in Section III, in ethernet switch, packets from HP class are always scheduled first.…”