Phase frequency detector of delay locked loop at high frequency

Khare, Kavita; Khare, N.; Deshpande, Pallavi S.; Kulhade, V.

doi:10.1109/smelec.2008.4770288

Cited by 19 publications

(1 citation statement)

References 2 publications

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“…A method for designing a DLL using domino logic has been presented [12]. The utilized PFD is capable of operating in the GHz frequency range.…”

Section: Introductionmentioning

confidence: 99%

Design of a delay locked loop with low power and high operating frequency range characteristics in 180-nm CMOS process

Saraji,

Ghorbani,

Anisheh

2023

Analog Integr Circ Sig Process

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Delay lock loop (DLL) is a key element in circuits such as clock synchronization, clock and data clock recovery. In this paper, new structures for phase frequency detector (PFD), charge pump (CP) and delay cell for low power applications are presented. A dynamic PFD based on CMOS inverter is proposed which has low power consumption and its operating frequency range is wide. The proposed CP is based on gate-driven and positive feedback techniques which has a good current matching. The delay cell uses the bulk-driven technique and has less power consumption than conventional structure. To assess the performance of the proposed structures, some simulations are performed in a 0.18 μm CMOS process with the supply voltage of 1.8 V. The simulation results show higher efficiency of the proposed structures than the existing structures in terms of accuracy and power consumption. The simulation results show that the maximum operating frequency of the PFD is 2 GHz. The mismatch between up and down currents of the CP is less than 0.3%. The power consumption of the proposed delay cell is 25% less than the conventional structure.

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“…A method for designing a DLL using domino logic has been presented [12]. The utilized PFD is capable of operating in the GHz frequency range.…”

Section: Introductionmentioning

confidence: 99%

Design of a delay locked loop with low power and high operating frequency range characteristics in 180-nm CMOS process

Saraji,

Ghorbani,

Anisheh

2023

Analog Integr Circ Sig Process

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show abstract

Modeling and Analysis of Low Power High-Speed Phase Detector and Phase Frequency Detector Using Nano Dimensional MOS Transistors at 16 nm, 22 nm, 32 nm

Valasa¹,

Tayal²

2022

Lecture Notes in Electrical Engineering

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Design of a CMOS PFD-CP module for a PLL

Anushkannan¹,

Mangalam²

2015

Sadhana

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This paper introduces a modified design of Phase frequency detector (PFD) with reduced dead zone and improved charge pump (CP) with reduced current mismatch for a Phase Locked Loop (PLL). Three modified PFD circuits are proposed, designed, simulated, and the results are analyzed considering dead zone as a constraint. Design of pass transistor logic network plays a part in the diminution of the dead zone. Further, an improved design of CP is proposed to reduce current mismatch. It is achieved by placing the single ended differential amplifier in currentvoltage feedback configuration which offers high output impedance. Simulations are performed using T-SPICE, implemented in IBM 0.13 µm technology under 1.3 V power supply. Results show that the modified PFD design has a dead zone of 0.3 ns and the current mismatch decrements to 0.1 µA in an improved CP design.

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Phase frequency detector of delay locked loop at high frequency

Cited by 19 publications

References 2 publications

Design of a delay locked loop with low power and high operating frequency range characteristics in 180-nm CMOS process

Design of a delay locked loop with low power and high operating frequency range characteristics in 180-nm CMOS process

Modeling and Analysis of Low Power High-Speed Phase Detector and Phase Frequency Detector Using Nano Dimensional MOS Transistors at 16 nm, 22 nm, 32 nm

Design of a CMOS PFD-CP module for a PLL

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