CMOS SRAM cell is very less power consuming and have less read and write time. Higher cell ratios can decrease the read and write time and improve stability. PMOS transistor with less width reduces the power consumption. This paper implements 6T SRAM cell with reduced read and write time, area and power consumption. It has been noticed often that increased memory capacity increases the bit-line parasitic capacitance which in turn slows down voltage sensing and make bit-line voltage swings energy expensive. This result in slower and more energy hungry memories.. In this paper Two SRAM cell is being designed for 4 Kb of memory core with supply voltage 1.8V. A technique of global bit line is used for reducing the power consumption and increasing the memory capacity.

Location awareness is the key to success to many location-based services applications such as indoor navigation, elderly tracking, emergency management, and so on. Trilateration-based localization using received signal strength measurements is widely used in wireless sensor network–based localization and tracking systems due to its simplicity and low computational cost. However, localization accuracy obtained with the trilateration technique is generally very poor because of fluctuating nature of received signal strength measurements. The reason behind such notorious behavior of received signal strength is dynamicity in target motion and surrounding environment. In addition, the significant localization error is induced during each iteration step during trilateration, which gets propagated in the next iterations. To address this problem, this article presents an improved trilateration-based architecture named Trilateration Centroid Generalized Regression Neural Network. The proposed Trilateration Centroid Generalized Regression Neural Network–based localization algorithm inherits the simplicity and efficiency of three concepts namely trilateration, centroid, and Generalized Regression Neural Network. The extensive simulation results indicate that the proposed Trilateration Centroid Generalized Regression Neural Network algorithm demonstrates superior localization performance as compared to trilateration, and Generalized Regression Neural Network algorithm.

Cancer is a significant cause of death worldwide. Early cancer detection is greatly aided by machine learning and artificial intelligence (AI) to gene microarray data sets (microarray data). Despite this, there is a significant discrepancy between the number of gene features in the microarray data set and the number of samples. Because of this, it is crucial to identify markers for gene array data. Existing feature selection algorithms, however, generally use long-standing, are limited to single-condition feature selection and rarely take feature extraction into account. This work proposes a Multi-stage algorithm for Biomedical Deep Feature Selection (MBDFS) to address this issue. In the first, three feature selection techniques are combined for thorough feature selection, and feature subsets are obtained; in the second, an unsupervised neural network is used to create the best representation of the feature subset to enhance final classification accuracy. Using a variety of metrics, including a comparison of classification results before and after feature selection and the performance of alternative feature selection methods, we evaluate MBDFS's efficacy. The experiments demonstrate that although MBDFS uses fewer features, classification accuracy is either unchanged or enhanced.

Most of the portable systems, such as cellular communication devices, and laptop computers operate from a limited power supply. Devices like cell phones have long idle times and operate in standby mode when not in use. Consequently, the extension of battery-based operation time is a significant design goal which can be made possible by controlling the leakage current flowing through the CMOS gate. This article reviews the off-state leakage mechanisms like weak inversion leakage, gate induced drain leakage and channel punchthrough current. Various circuit level techniques to reduce standby leakage and their design trade-off are discussed. Based on the surveyed techniques, a designer would be able to select the appropriate leakage optimization technique for a standby mode.

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