VLSI design and analysis of low power 6T SRAM cell using cadence tool

Abstract

CMOS SRAM cell is very less power consuming and have less read and write time. Higher cell ratios can decrease the read and write time and improve stability. PMOS transistor with less width reduces the power consumption. This paper implements 6T SRAM cell with reduced read and write time, area and power consumption. It has been noticed often that increased memory capacity increases the bit-line parasitic capacitance which in turn slows down voltage sensing and make bit-line voltage swings energy expensive. This result in slower and more energy hungry memories.. In this paper Two SRAM cell is being designed for 4 Kb of memory core with supply voltage 1.8V. A technique of global bit line is used for reducing the power consumption and increasing the memory capacity.

Design of Efficient Complex Gate using 45nm Technology

“… If A=B=C=D=0, all the PMOS gates (pull up gates) are in ON condition because PMOS will be in ON state for logic 0 input then all the PMOS circuits are allow the Vdd to pass through it. In pull-down network all the NMOS circuits are OFF for the logic 0 condition, so the Vdd which is passing through the pull-up network will not allowed by the pull down network, then total power passed to the output side through the pull up network then output will become high(I.e, Y=1) [9].  If A=0,B=1,C=0,D=0, here in pull up network A,C,D transistors are ON for logic 0 as input and B transistor is OFF for logic 1 as input [9] [8].…”

“…In pull-down network all the NMOS circuits are OFF for the logic 0 condition, so the Vdd which is passing through the pull-up network will not allowed by the pull down network, then total power passed to the output side through the pull up network then output will become high(I.e, Y=1) [9].  If A=0,B=1,C=0,D=0, here in pull up network A,C,D transistors are ON for logic 0 as input and B transistor is OFF for logic 1 as input [9] [8]. In pull down network only B transistor is ON condition as logic 1 as the input.…”

Comparative Study of 7T, 8T, 9T and 10T SRAM with Conventional 6T SRAM Cell Using 180 nm Technology

“…It consists of two access transistors M5 and M6 connected with common word line (WL). Each bit is stored in 4 transistors (M1, M2, M3, and M4) that form two cross coupled inverters [1,11]. As long as the pass-transistors are turned off, the cell keeps the store data in the cell.…”

“…But scaling the supply voltage effect the performance directly while scaling the threshold voltage shows highest impact in SNM [2]. In this paper, we have reviewed different SRAM cells like 7T SRAM [3,4], 8T SRAM [5,6], 9T SRAM [7,8] and 10T SRAM [9,10] based on read/write delay, power consumption and SNM compare to conventional 6T SRAM cell [1,[11][12][13].…”

Content-Addressable Memory System Using a Nanoelectromechanical Memory Switch

“…Conventional random-access memory devices, such as static random-access memory (SRAM) and dynamic random-access memory (DRAM), store data during a write cycle and read a stored memory during a read cycle. As a specific memory location, called the address, must be assigned during this process, sequential memory operations are inevitable for random-access memory devices [1][2][3][4][5].…”