Phase Noise Simulation and Modeling of ADPLL by SystemVerilog

Cell based synthesized low noise all digital frequency synthesizer, 0.13μm CMOS and FPGA implementations

“…The LPF Verilog code as shown in Listing 5.2 used in the FPGA is similar to the LPF Verilog code used in SystemVerilog simulation in [41]. The integral path is implemented as a bidirectional shift register that has a length of 288-bit and the proportional path is represented as 2-bit output.…”