Phenomenological model for "stress memorization" effect from a capped-poly process

Adam, Lahir Shaik; Chiu, C. K.; Huang, Min; Wang, X.; Wang, Y.; Singh, Saurabh; Chen, Y.; Bu, H.; Wu, Jeff

doi:10.1109/sispad.2005.201492

Cited by 6 publications

(4 citation statements)

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“…This could be originated from the different tensile strain. It has been reported that tensile strain from an SMT is obvious, specifically at the gate edge [6], [11]. Therefore, it is reasonable to deduce that the anomalously high gate tunneling current in Sample A is a result of higher tensile strain.…”

Section: Resultsmentioning

confidence: 91%

Anomalous Gate-Edge Leakage Induced by High Tensile Stress in NMOSFET

Liu

Huang

Lim

et al. 2008

IEEE Electron Device Lett.

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Anomalously high gate tunneling current, induced by high-tensile-stress memorization technique, is reported in this letter. Carrier-separation measurement method shows that the increased gate tunneling current is originated from the higher gate-to-source/drain (S/D) tunneling current, which worsens when channel length is getting shorter. Also, the device with enhanced tensile strain exhibits 9% higher gate-to-S/D overlapping capacitance. These data indicate that the anomalously high gate tunneling current could be attributed to the high tensile strain that induces the effects of excessive lightly doped dopant diffusion and higher gate-edge damage. The proposed inference is confirmed by channel hot-electron stress.Index Terms-Gate leakage current, MOSFETs, stress memorization technique (SMT).

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Section: Resultsmentioning

confidence: 91%

Anomalous Gate-Edge Leakage Induced by High Tensile Stress in NMOSFET

Liu

Huang

Lim

et al. 2008

IEEE Electron Device Lett.

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“…The SMT strain results from the residual stress memorized in the channel after nitride removal, rather than the initial mechanical stress created after nitride deposition as in the conventional CESL technique. 1,2 Many studies with the SMT process 3,[5][6][7] suggest that the process involves the following fundamental elements: S/D n-type dopant implantation, amorphized silicon implanted region, capping nitride deposition, S/D thermal annealing, and amorphous silicon transformation into recrystallized silicon with plastic silicon deformation. While the precise physics underlying the stress memorization is still unclear, recent studies have given some insight into the problem.…”

Section: Resultsmentioning

confidence: 99%

“…While the precise physics underlying the stress memorization is still unclear, recent studies have given some insight into the problem. Adam et al 5 proposed a phenomenological model to understand the stress memorization effect. A plastic deformation model is used to simulate such irreversible shape change in the polysilicon gate.…”

Section: Resultsmentioning

confidence: 99%

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Strained Silicon Technology: Mobility Enhancement and Improved Short Channel Effect Performance by Stress Memorization Technique on nFET Devices

Lu¹,

Huang²,

Luo³

et al. 2010

J. Electrochem. Soc.

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This paper presents a fundamental study of a stress memorization technique ͑SMT͒, which utilizes a capping nitride dielectric film to enhance negative channel field-effect transistor ͑nFET͒ device performance. SMT strain engineering is highly compatible with current standard complementary metal oxide semiconductor processes without introducing substantial additional complexity. In this work, we report that SMT-strained nFET exhibits a higher transconductance G m_lin , which indicates strain-induced electron mobility enhancement. The nFET short channel effect is also improved by the SMT process. Improved V t roll-off characteristics manifest itself and are shown to result from retarded junction diffusion as indicated by secondary-ion mass microscopy analysis. Finally, this work demonstrates that when combined with a strained contact etch stop layer ͑CESL͒ technique, SMT provides additional strain beyond that provided by the CESL, which results in further improved nFET performance.

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