Phonon-limited inversion layer electron mobility in extremely thin Si layer of silicon-on-insulator metal-oxide-semiconductor field-effect transistor

Abstract

Phonon-limited inversion layer electron mobility in extremely thin (100) Si layers of silicon-on-insulator field-effect transistors has been studied at 300 K using a relaxation time approximation and a one-dimensional self-consistent calculation. For the Si layer thickness tSi of more than approximately 5 nm, the mobility behavior as a function of an effective vertical electric field is found to be almost identical with that of bulk Si inversion layers. For a thickness of less than that, however, the mobility behavior is considerably affected by the change in the electronic structures due to a confinement effect. As the Si layer thickness decreases, the phonon-limited electron mobility μph increases to a maximum at tSi of ∼3 nm and decreases monotonically. The increase in mobility results from the increase of the fraction of electrons in the lowest energy subband that has a higher mobility than other subbands. The mobility decrease in the extremely thin tSi region is attributed to the enhancement of phonon scattering rates caused by a reduction of the spatial widths of the subbands.

Quantum-wire effects in trigate SOI MOSFETs

“…In each case one can observe the high electron concentration in the center of the silicon film or fin, corresponding to volume inversion. A direct consequence of volume inversion is the increase of inversion carrier mobility in devices with a thickness in the 5-10 nm range [19][20][21][22][23].…”

Ultimately thin double-gate SOI MOSFETs

“…From 20 nm down to 8 nm, the electron mobility tends to decrease more [41] or less [27]. Below 10 nm, several mechanisms are competing [33], [35], [42].…”

“…• The thinning process may degrade the film and generate new scattering centers [41], [45]. A promising conclusion is that the carrier mobility may increase in ultra-thin SOI films [33], [35], [42], with a maximum expected for 3.5 nm [33], [35]. Unfortunately, in current Si and SOI materials, surface roughness scattering strongly affects the motion of carriers [46]- [48].…”

Electron mobility enhancement in nanoscale silicon-on-insulator diffusion layers with high doping concentration of greater than 1 × 1018 cm−3 and silicon-on-insulator thickness of less than 10 nm

“…However, further miniaturization of device sizes leads to a serious issues called the short channel effects (SCE). 7 MOSFETs fabricated on silicon-oninsulator (SOI) layers, [8][9][10][11][12][13][14][15] hereafter referred to as SOI MOS-FETs, have been attracting growing interest because these MOSFETs possess stronger immunity to SCE and better suppression of variability than bulk MOSFETs; the better variability suppression in SOI MOSFETs is due to the reduced number of random discrete dopants in the channel. [16][17][18] However, the scaling of SOI MOSFETs to a channel length below 10 nm requires an SOI thickness, T SOI , of less than 5 nm.…”

“…In such nanoscale, extremely thin SOI (ETSOI) layers, numerous factors, otherwise ignored in traditional thick SOI MOS-FETs, affect the carrier transport. Scattering by both acoustic phonons 8,9,14,15 and interface roughness 13 is strongly influenced by the quantum confinement of carriers in nanoscale SOI layers. Thus far, the effects peculiar to extremely thin SOI layers have been studied in nanoscale ETSOI channels, as the transport in the channel dominates the entire transport in SOI MOSFETs.…”