Photoelectric heat effect induce instability on the negative bias temperature illumination stress for InGaZnO thin film transistors

Abstract

This paper investigates the instability of negative bias temperature in the dark and the illumination stresses for the InGaZnO thin film transistors. During the negative bias temperature illumination stress, properties exhibit an obvious negative threshold voltage shift and a significant degradation of subthreshold swing. The photoelectric heat effect that combined the effects of electric field, illumination, and temperature induces the generation of dangling bonds in the interface, resulting in an apparent degradation. It is related to the presence of light energy. Finally, this work also employs the capacitance-voltage measurement and recovery behavior to further clarify the mechanism of degradation behaviors.

Self-Aligned Top-Gate Amorphous Indium Zinc Oxide Thin-Film Transistors Exceeding Low-Temperature Poly-Si Transistor Performance

“…When transfer curves were measured at a drain–source voltage of 10.1 V for the device with 50 nm thick layer after the NBTIS, little V TH shift was observed along with nearly identical S values as shown in Figure c. Whereas the V TH shift of 1.0 V was observed after the PBTIS (Figure d), this V TH shift was small and comparable with the previous reports. − Because these NBTIS/PBTIS conditions were incomparably more severe than the normal operation conditions of AMOLEDs, our a-IZO TFTs are regarded stable enough even for the backplane device of commercial AMOLED. As a minor result of electrical stability test, hysteresis behavior was also observed as shown in Figure 6S in the Supporting Information, where only a little gate hysteresis is seen from our 30 and 50 nm thick a-IZO channel TFTs.…”

Thermal distribution in amorphous InSnZnO thin‐film transistor

“…For high-speed operation, TAOS thin-film transistors (TFTs) can be achieved by their high electron mobility. On the other hand, for reliability against extrinsic causes, it is well known that stabilities under illumination [5][6][7][8] and atmospheric condition are insufficient in TAOS TFT. Therefore, numerous studies have been focused on their sensitivities to improve reliability.…”

P‐5: Reduction of Mura Defects by Controlling the Mechanism of NBTIS of Amorphous‐Oxide TFTs

“…In particular, the threshold voltage stability play an important role in the dot mura issue [1]. And the Vth stability is important for flat-panel display applications because driving current stress is changed by Vth shifts and consequently pixel signal level/emission intensity is altered [2]. To further understand the origin of instability in a-IGZO TFTs under current stress, it is important to investigate the stability in a wide range of conditions such as negative bias, temperature, illumination stress (NBTIS) [3] and light shielding, for the defects such as oxygen deficiency often cause electron trapping and doping in oxide semiconductors and the formation is sensitive to the environment and the TFT structures [4].…”