Photomask quality assessment strategy at 90-nm technology node with aerial image simulation

Nagamura, Yoshikazu; Hosono, Kunihiro; Pang, Liang; Chan, K.; Tanaka, Yoshio

doi:10.1117/12.504209

Cited by 5 publications

(2 citation statements)

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“…Numerical Technology pioneered this field with the i-Virtual Stepper System™. [74][75][76][77][78][79][80][81][82][83] (later acquired by Synopsys, also led by the author). The Applied Materials AERA™ inspection system is an aerial-image-based mask-inspection system.…”

Section: Curvilinear Mask Inspectionmentioning

confidence: 99%

Inverse lithography technology: 30 years from concept to practical, full-chip reality

Pang

2021

J. Micro/Nanopattern. Mats. Metro.

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In lithography, optical proximity and process bias/effects need to be corrected to achieve the best wafer print. Efforts to correct for these effects started with a simple bias, adding a hammer head in line-ends to prevent line-end shortening. This first-generation correction was called rule-based optical proximity correction (OPC). Then, as chip feature sizes continued to shrink, OPC became more complicated and evolved to a model-based approach. Some extra patterns were added to masks, to improve the wafer process window, a measure of resilience to manufacturing variation. Around this time, the concept of inverse lithography technology (ILT), a mathematically rigorous inverse approach that determines the mask shapes that will produce the desired on-wafer results, was introduced. ILT has been explored and developed over the last three decades as the next generation of OPC, promising a solution to several challenges of advanced-node lithography, whether optical or extreme ultraviolet (EUV). Today, both OPC and ILT are part of an arsenal of lithography technologies called resolution enhancement technologies. Since OPC and ILT both involve computation, they are also considered as part of computational lithography. We explore the background and history of ILT and detail the significant milestones that have taken full-chip ILT from an academic concept to a practical production reality.

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Section: Curvilinear Mask Inspectionmentioning

confidence: 99%

Inverse lithography technology: 30 years from concept to practical, full-chip reality

Pang

2021

J. Micro/Nanopattern. Mats. Metro.

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“…The patterns on the advanced masks become smaller and more complicated than before. How to provide a qualified mask for wafer production with short turn-around time (TAT) is a key challenge for both mask makers and mask users 2,7,8 .…”

Section: Introductionmentioning

confidence: 99%

A simulation-based defect disposition flow for incoming mask quality assurance

et al. 2005

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As the industry transitions to 90 and 65nm photolithography, the increased complexity and costs of advanced photomask remain an industry focus. Mask makers and wafer fabs must develop new techniques in photomask inspection and quality control to improve turnaround time and ultimately the mask and wafer production yield. Specific to wafer fabs, this requires an increased focus on the incoming quality control techniques combined with improved communication with the mask shop.For incoming mask inspection "mask-level" defect inspection and dispositioning is no longer adequate. Aggressive OPC on PSM masks, combined with tighter CD requirements increases the burden on both machine and operator increasing the risk of mission a killer defect. For 90nm and beyond, simulation-based defect disposition techniques will be required to predict the wafer-level printing behavior and disposition the defects appropriately.A simulation-based defect disposition flow using Synopsys's i-Virtual Stepper System (iVSS) for incoming mask quality assurance is presented in this study. This paper will examine the feasibility of implementing such a flow from a waferfab operation point of view. What kind of benefits can be achieved and how it works will be also presented.

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