CMOS single-photon avalanche diodes (SPADs) have broken into the mainstream by enabling the adoption of imaging, timing, and security technologies in a variety of applications within the consumer, medical and industrial domains. The continued scaling of technology nodes creates many benefits but also obstacles for SPAD-based systems. Maintaining and/or improving upon the high-sensitivity, low-noise, and timing performance of demonstrated SPADs in custom technologies or well-established CMOS image sensor processes remains a challenge. In this paper, we present SPADs based on DPW/BNW junctions in a standard Bipolar-CMOS-DMOS (BCD) technology with results comparable to the state-of-the-art in terms of sensitivity and noise in a deep sub-micron process. Technology CAD (TCAD) simulations demonstrate the improved PDP with the simple addition of a single existing implant, which allows for an engineered performance without modifications to the process. The result is an 8.8 µm diameter SPAD exhibiting ∼2.6 cps/µm 2 DCR at 20 • C with 7 V excess bias. The improved structure obtains a PDP of 62 % and ∼4.2 % at 530 nm and 940 nm, respectively. Afterpulsing probability is ∼0.97 % and the timing response is 52 ps FWHM when measured with integrated passive quench/active recharge circuitry at 3V excess bias. Index Terms-Single-photon avalanche diodes (SPADs), Photon counting, depth-sensing, BCD, time-correlated single-photon counting(TCSPC), LIDAR, three-dimensional (3-D) ranging, FLIM, QRNG I. INTRODUCTION L ARGE-FORMAT single-photon avalanche diode (SPAD) arrays [1]-[3] are becoming ubiquitous in the timeresolved imaging domain for their utility in applications such as fluorescence lifetime imaging microscopy (FLIM),