Photonic Integrated Reconfigurable Linear Processors as Neural Network Accelerators

Marinis, Lorenzo De; Cococcioni, Marco; Liboiron-Ladouceur, Odile; Contestabile, G.; Castoldi, P.; Andriolli, N.

doi:10.3390/app11136232

Cited by 28 publications

(20 citation statements)

References 45 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Other impressive works of large-scale photonic integrated circuits can be found in the literature, however they are either non-universal [37][38][39][40][41][42][43][44][45][46][47][48][49], or have unknown performance in terms of losses [50][51][52][53][54][55][56][57][58][59][60]. [36] [20] This work [35] Silica SOI Si 3 N 4 FIG.…”

Section: Discussionmentioning

confidence: 99%

20-Mode Universal Quantum Photonic Processor

Taballione¹,

Anguita²,

Goede³

et al. 2022

Preprint

View full text Add to dashboard Cite

Integrated photonics is an essential technology for optical quantum computing. Universal, phasestable, reconfigurable multimode interferometers (quantum photonic processors) enable manipulation of photonic quantum states and are one of the main components of photonic quantum computers in various architectures. In this paper, we report the realization of the largest quantum photonic processor to date. The processor enables arbitrary unitary transformations on its 20 input modes with a fidelity of (F Haar = 97.4%, F Perm = 99.5%), an average optical loss of 2.9 dB/mode, and high-visibility quantum interference (V HOM = 98%). The processor is realized in Si 3 N 4 waveguides.

show abstract

Section: Discussionmentioning

confidence: 99%

20-Mode Universal Quantum Photonic Processor

Taballione¹,

Anguita²,

Goede³

et al. 2022

Preprint

View full text Add to dashboard Cite

show abstract

“…This necessitates the use of powerhungry optical amplification devices [7] and higher laser power at the input. Uncertainties due to fabrication-process variations-the analysis of which is beyond the scope of this paper-in the two DCs in an MZI can degrade the extinction ratio (ER) of the device which, in turn, will increase the loss and crosstalk in the output [15]. Yet, there is no prior work that analyzes the impact of optical loss and crosstalk noise in SP-NNs.…”

Section: Related Prior Workmentioning

confidence: 99%

“…Yet, there is no prior work that analyzes the impact of optical loss and crosstalk noise in SP-NNs. While the use of silicon nitride platform can help reduce the loss [15], the performance degradation due to coherent crosstalk in SP-NNs still remains unaddressed. Unlike in SP-NNs, optical loss and crosstalk noise have been widely studied in chip-scale Datacom photonic networks (e.g., [8] and [16]), showing signal integrity degradation and scalablity constraints in these networks due to optical loss and crosstalk noise.…”

Section: Related Prior Workmentioning

confidence: 99%

LoCI: An Analysis of the Impact of Optical Loss and Crosstalk Noise in Integrated Silicon-Photonic Neural Networks

Shafiee¹,

Banerjee²,

Chakrabarty³

et al. 2022

Preprint

View full text Add to dashboard Cite

Compared to electronic accelerators, integrated silicon-photonic neural networks (SP-NNs) promise higher speed and energy efficiency for emerging artificial-intelligence applications. However, a hitherto overlooked problem in SP-NNs is that the underlying silicon photonic devices suffer from intrinsic optical loss and crosstalk noise, the impact of which accumulates as the network scales up.Leveraging precise device-level models, this paper presents the first comprehensive and systematic optical loss and crosstalk modeling framework for SP-NNs. For an SP-NN case study with two hidden layers and 1380 tunable parameters, we show a catastrophic 84% drop in inferencing accuracy due to optical loss and crosstalk noise.

show abstract

“…In the roadmap towards low power and high density MAC engines, neuromorphic photonics promise to bring sub-fJ per MAC power efficiency with high compactness, while relying on an inherently parallel hardware that reduces the complexity growth [40]. Nevertheless, several challenges must be tackled to enable effective all-optical approaches for neuromorphic hardware, including the efficient largescale integration of many active and passive devices, and the reduction of losses and impairments, which may cause a significant accuracy drop (up to 70% in Mach-Zehnderbased coherent approaches) [41,42]. While considerable effort is put to overcome these issues [17,43,44], photonic analog processors are also emerging within hybrid photonic-electronic accelerators, being particularly suited to perform high-speed MAC operations for reduced-precision ANNs [14,23].…”

Section: A Reduced-precision Computing In Annmentioning

confidence: 99%

A Codesigned Integrated Photonic Electronic Neuron

Marinis

Catania

Contestabile

et al. 2022

IEEE J. Quantum Electron.

Self Cite

View full text Add to dashboard Cite

In the modern era of artificial intelligence, increasingly sophisticated artificial neural networks (ANNs) are implemented, which pose challenges in terms of execution speed and power consumption. To tackle this problem, recent research on reduced-precision ANNs opened the possibility to exploit analog hardware for neuromorphic acceleration. In this scenario, photonic-electronic engines are emerging as a short-medium term solution to exploit the high speed and inherent parallelism of optics for linear computations needed in ANN, while resorting to electronic circuitry for signal conditioning and memory storage.In this paper we introduce a precision-scalable integrated Photonic-Electronic Multiply-Accumulate Neuron (PEMAN). The proposed device relies on (i) an analog photonic engine to perform reduced-precision multiplications at high speed and low power, and (ii) an electronic front-end for accumulation and application of the nonlinear activation function by means of a nonlinear encoding in the analog-to-digital converter (ADC). The device has been numerically validated through cosimulations to perform multiply-accumulate operations (MAC). Simulations are based on the iSiPP50G SOI process for the photonic engine and a commercial 28 nm CMOS process for the electronic front-end. The PEMAN exhibits a multiplication accuracy of 6.1 ENOB up to 10 GMAC/s, while it can perform computations up to 56 GMAC/s with a reduced accuracy down to 2.1 ENOB. The device can trade off speed and power consumption with resolution, significantly outperforming its analog electronics counterparts both in terms of speed and power consumption.

show abstract

Photonic Integrated Reconfigurable Linear Processors as Neural Network Accelerators

Cited by 28 publications

References 45 publications

20-Mode Universal Quantum Photonic Processor

20-Mode Universal Quantum Photonic Processor

LoCI: An Analysis of the Impact of Optical Loss and Crosstalk Noise in Integrated Silicon-Photonic Neural Networks

A Codesigned Integrated Photonic Electronic Neuron

Contact Info

Product

Resources

About