Photonic network-on-chip architectures using multilayer deposited silicon materials for high-performance chip multiprocessors

Abstract

Integrated photonics has been slated as a revolutionary technology with the potential to mitigate the many challenges associated with on-and off-chip electrical interconnection networks. To date, all proposed chipscale photonic interconnects have been based on the crystalline silicon platform for CMOS-compatible fabrication. However, maintaining CMOS compatibility does not preclude the use of other CMOS-compatible silicon materials such as silicon nitride and polycrystalline silicon. In this work, we investigate utilizing devices based on these deposited materials to design photonic networks with multiple layers of photonic devices. We apply rigorous device optimization and insertion loss analysis on various network architectures, demonstrating that multilayer photonic networks can exhibit dramatically lower total insertion loss, enabling unprecedented bandwidth scalability. We show that significant improvements in waveguide propagation and waveguide crossing insertion losses resulting from using these materials enables the realization of topologies that were previously not feasible using only the single-layer crystalline silicon approaches.

A novel optical network on chip design for future generation of multiprocessors system on chip

“…Compared to the networks proposed by [3,10,15], the control flow is realized optically. In addition to allow a reduction of communication latency, WDM is used in order to concurrently propagate setup and acknowledgment signals, respectively through λ setup and λ acq wavelengths, which can help reducing contentions in the network.…”

“…If the destination is not reached, the control packet is re-converted in the optical domain and is transmitted to the next CU, depending on the availability of the optical resources, etc. Similarly to the networks proposed in [3,10,15], optical resources in the data flow network are reserved all along the setup packet path. Once the destination CU is reached, an optical acknowledgment packet P ack is sent back to the source processor (it is transmitted similarly to P setup ).…”

Designing Chip-Level Nanophotonic Interconnection Networks

“…An alternative would be to leverage the multiple nanophotonic devices layers available in monolithic back-end-of-line integration. Work by Biberman et al has shown how multilayer deposited devices can significantly impact the feasibility of various network architectures [42], and this illustrates the need for a design process that iterates across the architecture, microarchitecture, and physical design levels.…”

Hot-wire polysilicon waveguides with low deposition temperature

“…However, SOI is limited to lateral integration of photonics and electronics components. Vertical integration of photonic devices is usually performed through direct deposition of amorphous or polycrystalline silicon layers [3][4][5][6]. Multilayered integration is desirable due to several advantages such as reduced chip size and improved thermal isolation.…”

“…Multilayered integration is desirable due to several advantages such as reduced chip size and improved thermal isolation. Recently, there has been an increased interest in polysilicon waveguides due to their low cost and added design flexibility [3][4][5][6][7][8][9][10]. However, most of the reported polysilicon films were deposited or posttreated at high temperatures (≥900°C), e.g., [3,[6][7][8][9][10].…”