Physical design aware selection of energy-efficient and low-energy nanometer flip-flops

Alioto, Massimo; Consoli, Elio; Palumbo, G.

doi:10.1109/icm.2010.5696206

Cited by 3 publications

(1 citation statement)

References 23 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Among most widely logic blocks are flip flops (and latches that constitute them). Therefore, they play a very important role in setting the performance of digital ICs [41], [42].When estimating the power dissipation of a system, flip-flops are a main power consumption factor [39].…”

Section: Chapter 4 Proposed Design and Testing Approachmentioning

confidence: 99%

Design of Reliable and Efficient Flip-Flops for Subthreshold Operation Using Multi-Threshold MOSFETs and Transistor Sizing Technique

Shiran¹

View full text Add to dashboard Cite

This thesis addresses the challenge of designing reliable and energy-efficient subthreshold flip-flops. A dual-clock-phase flip-flop (TG-FF) and a single-clock-phase flip-flop (SP-FF) configurations are considered and their gradual design modifications are reported towards perfecting their yields at minimum cost in terms of energy consumption. In addition, the two optimized flip-flop designs are compared based on the criteria of static and dynamic energy consumptions, delay, and reliability in face of PVT variations.A 65 nm and a newer 28 nm CMOS technology kit were used during the course of this work. Multi-threshold MOSFETs and transistor sizing technique were incorporated for yield optimization. In general we were able to increase the flip-flops reliabilities to 100% at the nominal temperature and power supply condition, and in the worst-case around 90% in the extreme cold and -10% noise on the power supply. We also prove the overall superiority of the SP-FF compared to TG-FF. i Acknowledgment First and foremost, I would like to express my deep and sincere gratitude to my supervisor Professor Maitham Shams for the continuous support, understanding, kindness, and great guidance. During my studies, he not only helped me in my research but also he taught me in my life.

show abstract

Section: Chapter 4 Proposed Design and Testing Approachmentioning

confidence: 99%

Design of Reliable and Efficient Flip-Flops for Subthreshold Operation Using Multi-Threshold MOSFETs and Transistor Sizing Technique

Shiran¹

View full text Add to dashboard Cite

show abstract

Variation-aware Flip-Flop energy optimization for ultra low voltage operation

Kamakari

Nishizawa

Ishihara

et al. 2014

2014 27th IEEE International System-on-Chip Conference (SOCC)

View full text Add to dashboard Cite

This paper presents an energy optimization method for a Flip-Flop (FF) circuit in a presence of manufacturing process variation. The optimal FF circuit can be obtained by simultaneously scaling the supply voltage and the transistor size with achieving a specific high yield of the circuit. Lowering the supply voltage is one of the most effective approaches for decreasing the energy consumption of the circuit. However, the increased variation in nano scale semiconductor devices causes a malfunction of FFs especially for the very low voltage operation. Therefore, it is a challenging goal for the nano scale FFs to achieve the high yield and extremely low energy consumption simultaneously. This paper proposes an approximation method for accurately estimating a minimum possible operating voltage (V DDmin ) of FFs with a small number of Monte-Carlo trials. After that, for a given FF, we find a set of optimal supply voltage and the transistor sizes, which minimizes the energy consumption of the FF with achieving the specific high-sigma yield (e.g., 5σ yield). Post layout Monte-Carlo simulation results obtained using a commercial 28 nm process technology model demonstrate that the energy consumption of a FF optimized with our approach can be reduced by 17% at the best case with achieving 5σ yield.

show abstract

Implementation and Designing of Low Power SR Flip-Flop Using 45NM CMOS Technology

2017

View full text Add to dashboard Cite

The design of low-power devices is currently an important area of research due to an increase in demand for portable devices. Since the MOS device is widespread, there is a great need for circuits to consume less power, especially for portable and handheld devices. A memory element consumes 70 percent of the total power in an integrated circuit. As flip-flop is the primary place of memory elements to use on any portable device, a wide attention to reduce energy consumption flip-flop will help reducing energy consumption in a large IC. In this paper, we designed a flip-flop with CMOS logic; It consumes less energy than conventional gates designed. Switching transistors occurs when applied input clock is applied. Proposed SR flip-flop synchronization, 0.7V power dissipation transient analysis and SR flip-flop different applications. This flip-flop is implemented using 45 nm in virtuoso cadence.

show abstract

Physical design aware selection of energy-efficient and low-energy nanometer flip-flops

Cited by 3 publications

References 23 publications

Design of Reliable and Efficient Flip-Flops for Subthreshold Operation Using Multi-Threshold MOSFETs and Transistor Sizing Technique

Design of Reliable and Efficient Flip-Flops for Subthreshold Operation Using Multi-Threshold MOSFETs and Transistor Sizing Technique

Variation-aware Flip-Flop energy optimization for ultra low voltage operation

Implementation and Designing of Low Power SR Flip-Flop Using 45NM CMOS Technology

Contact Info

Product

Resources

About