Physical-Layer Modeling and System-Level Design of Chip-Scale Photonic Interconnection Networks

Abstract

Abstract-Photonic technology is becoming an increasingly attractive solution to the problems facing today's electronic chip-scale interconnection networks. Recent progress in silicon photonics research has enabled the demonstration of all the necessary optical building blocks for creating extremely highbandwidth density and energy-efficient links for on-chip and off-chip communications. From the feasibility and architecture perspective however, photonics represents a dramatic paradigm shift from traditional electronic network designs due to fundamental differences in how electronics and photonics function and behave. As a result of these differences, new modeling and analysis methods must be employed in order to properly realize a functional photonic chip-scale interconnect design. In this paper, we present a methodology for characterizing and modeling fundamental photonic building blocks which can subsequently be combined to form full photonic network architectures. We also describe a set of tools which can be utilized to assess the physical-layer and system-level performance properties of a photonic network. The models and tools are integrated in a novel open-source design and simulation environment. We present a case study of two different photonic networks-on-chip to demonstrate how our improved understanding and modeling of the physical-layer details of photonic communications can be used to better understand the system-level performance impact.Index Terms-Optical communications, optical crosstalk, optical losses, photonic interconnection networks, simulation software, system analysis and design.

Photonic Interconnection Network Architectures Using Wavelength-Selective Spatial Routing for Chip-Scale Communications

“…The partitioned-WDM network architecture is modeled and simulated in PhoenixSim, a chip-scale photonic network simulation environment [30]. All conducted simulations assumed a 2-cm × 2-cm 64-core CMP, which requires an 8 × 8 network.…”

“…Power parameters for optical devices are summarized in Table III. Details of the power simulation methodology that is employed by PhoenixSim can be found in [30]. Figure 15 depicts the network-level energy efficiency during the runtime of the application traces.…”

Scaling Star-Coupler-Based Optical Networks for Avionics Applications

“…PhoenixSim includes a library of electronic and photonic device models, including modulator [21], photodetector [22], and fiber connection, which can be tailored to measured parameters. New device models can also be easily added by extending existing device models [23]. The primary purpose of PhoenixSim is to reveal the system-level effects of integrating photonic devices into interconnection networks.…”

“…The primary purpose of PhoenixSim is to reveal the system-level effects of integrating photonic devices into interconnection networks. Recent work has focused on using PhoenixSim to show the benefits and trade-offs of optically enhanced chip-scale network architectures [23,24].…”

Modeling and Evaluation of Chip-to-Chip Scale Silicon Photonic Networks

“…Though initially architectures involving many components have been proposed [21], [33], only more sober designs might be considered feasible when all these effects are taken into account, as we explored in [9]. Furthermore, in real systems, links are generally utilized in a sporadic manner.…”