2015 International Conference on Emerging Research in Electronics, Computer Science and Technology (ICERECT) 2015
DOI: 10.1109/erect.2015.7499061
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Physical level design of floating point multiplier using Vedic Mathematics

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Cited by 2 publications
(4 citation statements)
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“…This can be easily demonstrated by the following diagram as shown in Figure 1 [3][4][5][6][7][8][9]. The result obtained will be J6J5J5J4J3J2J1J0 Each component of J has its own formula to give the conclusion of particular multiplication [7][8][9][10][11][12]. The process of obtaining components of J is clearly explained in the following Figures 2.…”
Section: Methodology and Results Discussionmentioning
confidence: 93%
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“…This can be easily demonstrated by the following diagram as shown in Figure 1 [3][4][5][6][7][8][9]. The result obtained will be J6J5J5J4J3J2J1J0 Each component of J has its own formula to give the conclusion of particular multiplication [7][8][9][10][11][12]. The process of obtaining components of J is clearly explained in the following Figures 2.…”
Section: Methodology and Results Discussionmentioning
confidence: 93%
“…The obtained result would be J4J3J2J1J0. As similar to the 4-bit multiplication these components of J also will have their formulas to reach the final destiny of multiplication [9][10][11][12][13][14]. The formulas used in the process are listed below.…”
Section: Methodology and Results Discussionmentioning
confidence: 99%
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